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121. 发明申请

US20110057145A1 METHOD FOR PREPARING DENDRIMER-MODIFIED, MAGNETIC FINE PARTICLES 审中-公开
标题翻译：制备改性改性的磁性颗粒的方法
公开(公告)号：US20110057145A1
公开(公告)日：2011-03-10
申请号：US12876562
申请日：2010-09-07
申请人： Tadashi Matsunaga , Tsuyoshi Tanaka , Keiichi Hatakeyama , Takeo Tanaami , Hitoshi Wake , Tomoyuki Taguchi , Takeyuki Mogi
发明人： Tadashi Matsunaga , Tsuyoshi Tanaka , Keiichi Hatakeyama , Takeo Tanaami , Hitoshi Wake , Tomoyuki Taguchi , Takeyuki Mogi
IPC分类号： H01F1/00
CPC分类号： H01F1/42
摘要： There is provided a method for preparing dendrimer-modified magnetic fine particles wherein such particles can be made within a shorter time and more inexpensively than in the above-stated prior art processes and lot-to-lot variations in properties are lessened. The method for preparing dendrimer-fixed magnetic fine particles comprises the steps of providing magnetic particles having a functional group at a surface thereof, providing a dendrimer having a functional group at a base end portion thereof and synthesized to a desired generation and binding the functional group of the magnetic particles and the functional group of the dendrimer directly or indirectly through a crosslinking agent.
摘要翻译：提供了一种制备树枝状聚合物改性的磁性细颗粒的方法，其中这种颗粒可以在比上述现有技术方法更短的时间和更廉价的情况下制备，并且批次间的性质变化减少。制备树枝状大分子固定磁性微粒的方法包括以下步骤：在其表面提供具有官能团的磁性颗粒，提供在其基端部分具有官能团的树枝状聚合物，并合成所需的一代并结合官能团的磁性颗粒和树枝状聚合物的官能团直接或间接地通过交联剂。

122. 发明申请

US20110049574A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110049574A1
公开(公告)日：2011-03-03
申请号：US12917994
申请日：2010-11-02
申请人： Hiroaki UENO , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Hiroaki UENO , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/452
摘要： A semiconductor device includes a first group III-V nitride semiconductor layer, a second group III-V nitride semiconductor layer having a larger band gap than the first group III-V nitride semiconductor layer and at least one ohmic electrode successively formed on a substrate. The ohmic electrode is formed so as to have a base portion penetrating the second group III-V nitride semiconductor layer and reaching a portion of the first group III-V nitride semiconductor layer disposed beneath a two-dimensional electron gas layer. An impurity doped layer is formed in portions of the first group III-V nitride semiconductor layer and the second group III-V nitride semiconductor layer in contact with the ohmic electrode.
摘要翻译：半导体器件包括第一III-V族氮化物半导体层，具有比第一III-V族氮化物半导体层更大的带隙的第二III-V族氮化物半导体层和在衬底上依次形成的至少一个欧姆电极。欧姆电极形成为具有穿透第二III-V族氮化物半导体层并且到达设置在二维电子气体层下方的第一III-V族氮化物半导体层的一部分的基极部分。在与欧姆电极接触的第一III-V族氮化物半导体层和第二III-V族氮化物半导体层的部分中形成杂质掺杂层。

123. 发明申请

US20110012173A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110012173A1
公开(公告)日：2011-01-20
申请号：US12867427
申请日：2009-01-23
申请人： Hidekazu Umeda , Masahiro Hikita , Tetsuzo Ueda , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Hidekazu Umeda , Masahiro Hikita , Tetsuzo Ueda , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L29/12
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/41766 , H01L29/4236 , H01L29/432 , H01L29/66462
摘要： A semiconductor device includes an undoped GaN layer (103) formed on a substrate (101), an undoped AlGaN layer (104) formed on the undoped GaN layer (103) and having a band gap energy larger than that of the undoped GaN layer (103), a p-type AlGaN layer (105) and a high-concentration p-type GaN layer (106) formed on the undoped AlGaN layer (104), and an n-type AlGaN layer (107) formed on the high-concentration p-type GaN layer (106). A gate electrode (112) which makes ohmic contact with the high-concentration p-type GaN layer (106) is formed on the high-concentration p-type GaN layer (106) in a region thereof exposed through an opening (107a) formed in the n-type AlGaN layer (107).
摘要翻译：半导体器件包括形成在衬底（101）上的未掺杂的GaN层（103），形成在未掺杂的GaN层（103）上并且具有比未掺杂的GaN层的带隙能量大的带隙能量的未掺杂的AlGaN层（104） 103），形成在未掺杂的AlGaN层（104）上的p型AlGaN层（105）和高浓度p型GaN层（106）以及形成在高掺杂AlGaN层上的n型AlGaN层（107）浓度p型GaN层（106）。在高浓度p型GaN层（106）上形成与高浓度p型GaN层（106）欧姆接触的栅电极（112），其形成在通过形成的开口（107a）的部分露出的区域在n型AlGaN层（107）中。

124. 发明申请

US20100320559A1 SEMICONDUCTOR DEVICE INCLUDING INDEPENDENT ACTIVE LAYERS AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：包括独立活性层的半导体器件及其制造方法
公开(公告)号：US20100320559A1
公开(公告)日：2010-12-23
申请号：US12853700
申请日：2010-08-10
申请人： Yutaka HIROSE , Tsuyoshi Tanaka
发明人： Yutaka HIROSE , Tsuyoshi Tanaka
IPC分类号： H01L27/06 , H01L21/77 , H01L23/538
CPC分类号： H01L27/0605 , H01L21/84 , H01L27/1203 , H01L29/2003 , H01L29/66462 , H01L29/7787
摘要： A semiconductor device includes a semiconductor substrate of n-type silicon including, in an upper portion thereof, a first polarity inversion region and a second polarity inversion regions spaced from each other and doped with a p-type impurity. A first HFET including a first active layer and a second HFET including a second active layer both made of a group III-V nitride semiconductor are independently formed on the respective polarity inversion regions in the semiconductor substrate, and the HFETs are electrically connected to each other through interconnects.
摘要翻译：半导体器件包括n型硅的半导体衬底，在其上部包括彼此间隔开并掺杂有p型杂质的第一极性反转区域和第二极性反转区域。包括第一有源层的第一HFET和包括由III-V族氮化物半导体构成的第二有源层的第二HFET独立地形成在半导体衬底中的相应极性反转区域上，并且HFET彼此电连接通过互连。

125. 发明授权

US07683399B2 Transistor 有权
标题翻译：晶体管
公开(公告)号：US07683399B2
公开(公告)日：2010-03-23
申请号：US11758304
申请日：2007-06-05
申请人： Hidetoshi Ishida , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Hidetoshi Ishida , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L31/0328
CPC分类号： H01L29/7787 , H01L29/045 , H01L29/0891 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/452
摘要： There is provided a normally-off type transistor made of a nitride semiconductor. The transistor includes; an undoped GaN layer which forms a channel region; an undoped Al0.2Ga0.8N layer which is formed on the undoped GaN layer and has a band gap larger than that of the undoped GaN layer; a p-type Al0.2Ga0.8N control layer which is formed on the undoped Al0.2Ga0.8N layer, has a p-type conductivity and forms a control region; an Ni gate electrode which contacts with the p-type Al0.2Ga0.8N control layer; a Ti/Al source electrode and a Ti/Al drain electrode which are formed beside the p-type Al0.2Ga0.8N control layer; and an Ni ohmic electrode which is connected to the undoped GaN layer and serves as a hole absorbing electrode. With this transistor, it is possible to achieve a large-current operation and a high switching speed.
摘要翻译：提供了由氮化物半导体制成的常关型晶体管。晶体管包括：形成沟道区的未掺杂GaN层; 未掺杂的Al0.2Ga0.8N层，其形成在未掺杂的GaN层上，并且具有比未掺杂的GaN层的带隙大的带隙; 形成在未掺杂的Al0.2Ga0.8N层上的p型Al0.2Ga0.8N控制层具有p型导电性并形成控制区; 与p型Al0.2Ga0.8N控制层接触的Ni栅电极; 形成在p型Al0.2Ga0.8N控制层旁边的Ti / Al源电极和Ti / Al漏电极; 以及连接到未掺杂的GaN层并用作空穴吸收电极的Ni欧姆电极。利用该晶体管，可以实现大电流动作和高切换速度。

126. 发明授权

US07663161B2 Transistor for preventing current collapse and having improved leakage current characteristics and method for fabricating the same 有权
标题翻译：用于防止电流塌陷并具有改善的漏电流特性的晶体管及其制造方法
公开(公告)号：US07663161B2
公开(公告)日：2010-02-16
申请号：US11939899
申请日：2007-11-14
申请人： Kazuhiro Kaibara , Masahiro Hikita , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Kazuhiro Kaibara , Masahiro Hikita , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L29/739 , H01L29/732 , H01L29/22 , H01L33/00 , H01L29/06
CPC分类号： H01L29/7787 , H01L29/1066 , H01L29/2003 , H01L29/41766 , H01L29/432
摘要： A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a second p-type semiconductor layer formed on the first p-type semiconductor layer. The first p-type semiconductor layer is separated from a drain electrode by interposing therebetween a first groove having a bottom composed of the first region, and from a source electrode by interposing therebetween a second groove having a bottom composed of the second region.
摘要翻译：晶体管包括：第一半导体层和具有第一区域和第二区域的第二半导体层，其顺序地形成在衬底上; 形成在除了第一和第二区域之外的第二半导体层的区域上的第一p型半导体层; 以及形成在第一p型半导体层上的第二p型半导体层。第一p型半导体层与漏电极分离，其间具有由第一区域构成的底部的第一沟槽和源极电极之间插入具有由第二区域构成的底部的第二沟槽。

127. 发明授权

US07603214B2 In-vehicle input unit 有权
标题翻译：车载输入单元
公开(公告)号：US07603214B2
公开(公告)日：2009-10-13
申请号：US11432530
申请日：2006-05-12
申请人： Tsuyoshi Tanaka , Yasushi Ishiai
发明人： Tsuyoshi Tanaka , Yasushi Ishiai
IPC分类号： G05G1/02 , G05G1/08
CPC分类号： B60K37/06 , B60K2350/928 , G02B27/01
摘要： An in-vehicle input unit is provided which includes: a head-up display which projects a hierarchical menu for operating a plurality of pieces of in-vehicle equipment onto a windshield in front of a driver's seat, and displays the hierarchical menu as a virtual image ahead of the windshield; and a plurality of switches which are disposed in a steering wheel so that several switches adjoin and surround one central switch, in which the head-up display displays selection items on the hierarchical menu as the virtual image so that the selection items correspond one to one to the plurality of switches disposed in the steering wheel.
摘要翻译：提供一种车载输入单元，其包括：平视显示器，其将用于操作多个车载设备的分层菜单投射到驾驶员座椅前方的挡风玻璃上，并将该分层菜单显示为虚拟挡风玻璃前方的图像; 以及多个开关，其设置在方向盘中，使得几个开关邻接并围绕一个中央开关，其中平视显示器将分层菜单上的选择项目显示为虚拟图像，使得选择项目对应于一对一到设置在方向盘中的多个开关。

128. 发明授权

US07577770B2 System and method for performance monitoring and reconfiguring computer system with hardware monitor 失效
标题翻译：使用硬件监视器对性能监控和重新配置计算机系统的系统和方法
公开(公告)号：US07577770B2
公开(公告)日：2009-08-18
申请号：US11771397
申请日：2007-06-29
申请人： Tsuyoshi Tanaka , Yoshiki Murakami
发明人： Tsuyoshi Tanaka , Yoshiki Murakami
IPC分类号： G06F3/00
CPC分类号： G06F11/3419 , G06F11/3466 , G06F2201/87 , G06F2201/88
摘要： A judgment is made quickly about whether or not it is a memory or a chipset that is causing a performance bottleneck in an application program. A computer system of this invention includes at least one CPU, a controller that connects the CPU to a memory and to an I/O interface, in which the controller includes a response time measuring unit, which receives a request to access the memory and measures a response time taken to respond to the memory access request, a frequency counting unit, which measures an issue count of the memory access request, a measurement result storing unit, which stores a measurement result associating the response time with the corresponding issue count, and a measurement result control unit which outputs the measurement result stored in the measurement result storing unit when receiving a measurement result read request.
摘要翻译：快速判断是否是在应用程序中导致性能瓶颈的存储器或芯片组。本发明的计算机系统包括至少一个CPU，将CPU连接到存储器和I / O接口的控制器，其中控制器包括响应时间测量单元，其接收访问存储器的请求并测量对存储器访问请求进行响应的响应时间;测量存储器访问请求的发行次数的频率计数单元;存储将响应时间与相应发行次数相关联的测量结果的测量结果存储单元;以及测量结果控制单元，当接收到测量结果读取请求时，输出存储在测量结果存储单元中的测量结果。

129. 发明授权

US07528673B2 Oscillator circuit and semiconductor device having oscillator circuit 失效
标题翻译：振荡电路和具有振荡电路的半导体器件
公开(公告)号：US07528673B2
公开(公告)日：2009-05-05
申请号：US11225451
申请日：2005-09-13
申请人： Akihisa Shibuya , Koji Tsukamoto , Yasuhide Shimizu , Tsuyoshi Tanaka
发明人： Akihisa Shibuya , Koji Tsukamoto , Yasuhide Shimizu , Tsuyoshi Tanaka
IPC分类号： H03K3/26
CPC分类号： H03L7/02
摘要： An oscillator circuit having a closed loop connection, including: an oscillator for generating an output signal oscillating at a frequency corresponding to a control signal; a frequency/voltage converter for generating a detection signal having a voltage corresponding to a frequency of the output signal; a difference detector for generating a difference signal indicating a difference between the detection signal and a reference signal; and an integrator for generating the control signal by integrating the difference signal.
摘要翻译：一种具有闭环连接的振荡器电路，包括：振荡器，用于产生以对应于控制信号的频率振荡的输出信号; 用于产生具有与输出信号的频率对应的电压的检测信号的频率/电压转换器; 差分检测器，用于产生指示检测信号和参考信号之间的差的差信号; 以及积分器，用于通过积分差分信号来产生控制信号。

130. 发明授权

US07528423B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07528423B2
公开(公告)日：2009-05-05
申请号：US11681408
申请日：2007-03-02
申请人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
发明人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
IPC分类号： H01L31/072 , H01L31/109
CPC分类号： H01L29/7786 , H01L29/2003
摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.
摘要翻译：本发明的一个目的是提供一种可以同时实现HFET的常闭模式和改进Imax的半导体器件，并进一步实现gm的改善和栅极漏电流的减小。为了在栅电极正下方的基板11的操作层12上保持薄的阻挡层13，主要用于实现常关模式并且还实现了高的Imax，它被配置成使得厚度可以通过栅极和源极区域之间以及栅极和漏极区域之间的半导体层17来增加阻挡层13。因此，与设置阻挡层的厚度均匀的FET相比，可以实现常闭模式和Imax的改善。介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而可以实现gm的改善和栅极漏电流的减小。

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