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1. 发明授权

US07663161B2 Transistor for preventing current collapse and having improved leakage current characteristics and method for fabricating the same 有权
标题翻译：用于防止电流塌陷并具有改善的漏电流特性的晶体管及其制造方法
公开(公告)号：US07663161B2
公开(公告)日：2010-02-16
申请号：US11939899
申请日：2007-11-14
申请人： Kazuhiro Kaibara , Masahiro Hikita , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Kazuhiro Kaibara , Masahiro Hikita , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L29/739 , H01L29/732 , H01L29/22 , H01L33/00 , H01L29/06
CPC分类号： H01L29/7787 , H01L29/1066 , H01L29/2003 , H01L29/41766 , H01L29/432
摘要： A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a second p-type semiconductor layer formed on the first p-type semiconductor layer. The first p-type semiconductor layer is separated from a drain electrode by interposing therebetween a first groove having a bottom composed of the first region, and from a source electrode by interposing therebetween a second groove having a bottom composed of the second region.
摘要翻译：晶体管包括：第一半导体层和具有第一区域和第二区域的第二半导体层，其顺序地形成在衬底上; 形成在除了第一和第二区域之外的第二半导体层的区域上的第一p型半导体层; 以及形成在第一p型半导体层上的第二p型半导体层。第一p型半导体层与漏电极分离，其间具有由第一区域构成的底部的第一沟槽和源极电极之间插入具有由第二区域构成的底部的第二沟槽。

2. 发明申请

US20120126290A1 NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：氮化物半导体器件及其制造方法
公开(公告)号：US20120126290A1
公开(公告)日：2012-05-24
申请号：US13360275
申请日：2012-01-27
申请人： Yasuhiro UEMOTO , Masahiro Hikita , Tetsuzo Ueda , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Yasuhiro UEMOTO , Masahiro Hikita , Tetsuzo Ueda , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L29/778
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/7783
摘要： A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.
摘要翻译：氮化物半导体器件包括：第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更宽的带隙的第二氮化物半导体层; 以及形成在所述第二氮化物半导体层上的第三氮化物半导体层。位于栅电极下方的第三氮化物半导体层的区域形成有具有p型导电性的控制区域，以及位于栅电极与源电极和漏极之间的第三氮化物半导体层的区域形成有具有比控制区域更高的电阻的高电阻区域。

3. 发明授权

US07898002B2 Nitride semiconductor device and method for fabricating the same 有权
标题翻译：氮化物半导体器件及其制造方法
公开(公告)号：US07898002B2
公开(公告)日：2011-03-01
申请号：US11890480
申请日：2007-08-07
申请人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L21/337 , H01L21/335
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/432 , H01L29/66462
摘要： A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer formed over the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a larger band gap energy than the first nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and including a p-type nitride semiconductor with at least a single-layer structure; a gate electrode formed on the third nitride semiconductor layer; and a source electrode and a drain electrode formed in regions located on both sides of the gate electrode, respectively. The third nitride semiconductor layer has a thickness greater in a portion below the gate electrode than in a portion below the side of the gate electrode.
摘要翻译：氮化物半导体器件包括：衬底; 形成在所述基板上的第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更大的带隙能量的第二氮化物半导体层; 形成在所述第二氮化物半导体层上并且包括具有至少单层结构的p型氮化物半导体的第三氮化物半导体层; 形成在所述第三氮化物半导体层上的栅极; 以及分别形成在位于栅电极两侧的区域中的源电极和漏电极。所述第三氮化物半导体层的厚度比所述栅极电极侧的部分的厚度大。

4. 发明申请

US20100327293A1 FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20100327293A1
公开(公告)日：2010-12-30
申请号：US12880704
申请日：2010-09-13
申请人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L29/20
CPC分类号： H01L29/7786 , H01L29/0843 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/66462 , H01L29/7783
摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.
摘要翻译：依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。栅电极与重掺杂的p型GaN层形成欧姆接触。源电极和漏电极设置在未掺杂的AlGaN层上。通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

5. 发明申请

US20090121775A1 TRANSISTOR AND METHOD FOR OPERATING THE SAME 有权
标题翻译：晶体管及其操作方法
公开(公告)号：US20090121775A1
公开(公告)日：2009-05-14
申请号：US11995040
申请日：2006-06-27
申请人： Daisuke Ueda , Tsuyoshi Tanaka , Yasuhiro Uemoto , Tetsuzo Ueda , Manabu Yanagihara , Masahiro Hikita , Hiroaki Ueno
发明人： Daisuke Ueda , Tsuyoshi Tanaka , Yasuhiro Uemoto , Tetsuzo Ueda , Manabu Yanagihara , Masahiro Hikita , Hiroaki Ueno
IPC分类号： H01L29/207 , H03K17/687
CPC分类号： H01L29/739 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/7786
摘要： In a transistor, an AlN buffer layer 102, an undoped GaN layer 103, an undoped AlGaN layer 104, a p-type control layer 105, and a p-type contact layer 106 are formed in this order on a sapphire substrate 101. The transistor further includes a gate electrode 110 in ohmic contact with the p-type contact layer 106, and a source electrode 108 and a drain electrode 109 provided on the undoped AlGaN layer 104. By applying a positive voltage to the p-type control layer 105, holes are injected into a channel to increase a current flowing in the channel.
摘要翻译：在晶体管中，在蓝宝石衬底101上依次形成AlN缓冲层102，未掺杂的GaN层103，未掺杂的AlGaN层104，p型控制层105和p型接触层106。晶体管还包括与p型接触层106欧姆接触的栅电极110以及设置在未掺杂的AlGaN层104上的源电极108和漏极109.通过向p型控制层105施加正电压，孔被注入到通道中以增加在通道中流动的电流。

6. 发明申请

US20080087915A1 Nitride semiconductor device and method for fabricating the same 有权
标题翻译：氮化物半导体器件及其制造方法
公开(公告)号：US20080087915A1
公开(公告)日：2008-04-17
申请号：US11878352
申请日：2007-07-24
申请人： Yasuhiro Uemoto , Masahiro Hikita , Tetsuzo Ueda , Tsuyoshi Tanaka , Daisuke Ueda
发明人： Yasuhiro Uemoto , Masahiro Hikita , Tetsuzo Ueda , Tsuyoshi Tanaka , Daisuke Ueda
IPC分类号： H01L21/336 , H01L29/772 , H01L31/00
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/7783
摘要： A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider band gap than the first nitride semiconductor layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. A region of the third nitride semiconductor layer located below the gate electrode is formed with a control region having a p-type conductivity, and a region of the third nitride semiconductor layer located between the gate electrode and each of the source electrode and the drain electrode is formed with a high resistive region having a higher resistance than the that of the control region.
摘要翻译：氮化物半导体器件包括：第一氮化物半导体层; 形成在所述第一氮化物半导体层上并且具有比所述第一氮化物半导体层更宽的带隙的第二氮化物半导体层; 以及形成在所述第二氮化物半导体层上的第三氮化物半导体层。位于栅电极下方的第三氮化物半导体层的区域形成有具有p型导电性的控制区域，以及位于栅电极与源电极和漏极之间的第三氮化物半导体层的区域形成有具有比控制区域更高的电阻的高电阻区域。

7. 发明授权

US07217960B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07217960B2
公开(公告)日：2007-05-15
申请号：US11325340
申请日：2006-01-05
申请人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
发明人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
IPC分类号： H01L33/00
CPC分类号： H01L29/7786 , H01L29/2003
摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.
摘要翻译：本发明的一个目的是提供一种半导体器件，其可以同时实现HFET的常闭模式和改进的最大值，并进一步实现gm的改善和栅极漏电流的减小。为了在栅电极正下方的基板11的操作层12上保持薄势垒层13，主要用于实现常关模式并且还实现高I max，配置成使得栅极和源极区域之间以及栅极和漏极区域之间的半导体层17可以增加阻挡层13的厚度。因此与阻挡层的厚度被设计为均匀的FET相比，可以实现常关模式和I 的改善。介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而改善gm和栅极漏电流的减小可以实现。

8. 发明授权

US08592866B2 Transistor 有权
标题翻译：晶体管
公开(公告)号：US08592866B2
公开(公告)日：2013-11-26
申请号：US11600102
申请日：2006-11-16
申请人： Manabu Yanagihara , Masahiro Hikita , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Manabu Yanagihara , Masahiro Hikita , Tetsuzo Ueda , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L29/1066 , H01L29/2003 , H01L29/4175 , H01L29/432 , H01L29/66462
摘要： A transistor includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer and has a band gap larger than that of the first semiconductor layer, a control layer formed on the second semiconductor layer and contains p-type impurities, a gate electrode formed in contact with at least part of the control layer and a source electrode and a drain electrode formed on both sides of the control layer, respectively. A third semiconductor layer made of material having a lower etch rate than that of the control layer is formed between the control layer and the second semiconductor layer.
摘要翻译：晶体管包括形成在基板上的第一半导体层，形成在第一半导体层上并具有比第一半导体层的带隙大的带隙的第二半导体层，形成在第二半导体层上并包含p型杂质，形成为与控制层的至少一部分接触的栅极电极以及分别形成在控制层两侧的源电极和漏电极。在控制层和第二半导体层之间形成由蚀刻率低于控制层的材料制成的第三半导体层。

9. 发明授权

US08264002B2 Field-effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08264002B2
公开(公告)日：2012-09-11
申请号：US12880704
申请日：2010-09-13
申请人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
发明人： Masahiro Hikita , Tetsuzo Ueda , Manabu Yanagihara , Yasuhiro Uemoto , Tsuyoshi Tanaka
IPC分类号： H01L29/66 , H01L21/02 , H01L29/78
CPC分类号： H01L29/7786 , H01L29/0843 , H01L29/1066 , H01L29/2003 , H01L29/432 , H01L29/66462 , H01L29/7783
摘要： An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.
摘要翻译：依次形成AlN缓冲层，未掺杂的GaN层，未掺杂的AlGaN层，p型GaN层和重掺杂的p型GaN层。栅电极与重掺杂的p型GaN层形成欧姆接触。源电极和漏电极设置在未掺杂的AlGaN层上。通过在未掺杂的AlGaN层和未掺杂的GaN层和p型GaN层之间的界面处产生的二维电子气在栅极区域中形成pn结，从而可以提高栅极电压。

10. 发明授权

US07528423B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07528423B2
公开(公告)日：2009-05-05
申请号：US11681408
申请日：2007-03-02
申请人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
发明人： Hiroaki Ueno , Tetsuzo Ueda , Yasuhiro Uemoto , Daisuke Ueda , Tsuyoshi Tanaka , Manabu Yanagihara , Yutaka Hirose , Masahiro Hikita
IPC分类号： H01L31/072 , H01L31/109
CPC分类号： H01L29/7786 , H01L29/2003
摘要： It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in Imax, and further achieve an improvement in gm and a reduction in gate leakage current. In order to keep a thin barrier layer 13 on an operation layer 12 of a substrate 11 directly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high Imax, it is configured in such a way that a thickness of the barrier layer 13 can be increased by the semiconductor layer 17 between gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Imax as compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating film 18 with a dielectric constant higher than that of the barrier layer is further inserted between a gate electrode 16 and the barrier layers 13, so that an improvement in gm and a reduction in gate leakage current can be achieved.
摘要翻译：本发明的一个目的是提供一种可以同时实现HFET的常闭模式和改进Imax的半导体器件，并进一步实现gm的改善和栅极漏电流的减小。为了在栅电极正下方的基板11的操作层12上保持薄的阻挡层13，主要用于实现常关模式并且还实现了高的Imax，它被配置成使得厚度可以通过栅极和源极区域之间以及栅极和漏极区域之间的半导体层17来增加阻挡层13。因此，与设置阻挡层的厚度均匀的FET相比，可以实现常闭模式和Imax的改善。介电常数高于阻挡层的绝缘膜18进一步插入在栅电极16和阻挡层13之间，从而可以实现gm的改善和栅极漏电流的减小。

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