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121. 发明申请

US20060220753A1 Oscillator array with row and column control 有权
标题翻译：具有行和列控制的振荡器阵列
公开(公告)号：US20060220753A1
公开(公告)日：2006-10-05
申请号：US11095895
申请日：2005-03-31
申请人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
发明人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
IPC分类号： H03K3/03
CPC分类号： G06F7/588 , H03K3/0315 , H03K3/84
摘要： A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.
摘要翻译：提供了一种电路拓扑结构，可用于创建由通用控制输入确定的不同频率运行的单独调谐的振荡器阵列，以及易于管理的多个组件的设计尺寸变化。提供了一列列和列排列的振荡器阵列。列中的每个振荡器都基于列中的其他振荡器是独特的，基于振荡器和扇出的级数，使得每个振荡器将以唯一的频率工作。阵列中不同列的振荡器可能会通过对这些振荡器的选择的共同设置以及列中的振荡器的物理顺序而不同，以进一步降低注入锁定的可能性。基本延迟单元为每列振荡器提供选择，使得每列可被编程为以与其邻居不同的频率工作。

122. 发明申请

US20060093047A1 Circuit to reduce transient current swings during mode transitions of high frequency/high power chips 失效
标题翻译：在高频/高功率芯片的模式转换期间减少瞬态电流摆幅的电路
公开(公告)号：US20060093047A1
公开(公告)日：2006-05-04
申请号：US10981154
申请日：2004-11-04
申请人： David Boerstler , Eskinder Hailu , Mack Riley , Michael Wang
发明人： David Boerstler , Eskinder Hailu , Mack Riley , Michael Wang
IPC分类号： H04L25/00
CPC分类号： H03K23/662 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.
摘要翻译：提供了一种方法，装置和计算机程序以减少模式转换期间的瞬态电流摆动。传统上，芯片上的瞬态电源电压波动占大部分电源。串联电感和电阻的数量通常最小化，同时在电源电压和地之间增加大的去耦电容。然而，不能实现串联电感和电阻的降低的情况。因此，为了帮助控制瞬态电流摆动，以受控的方式执行时钟频率的降低。

123. 发明申请

US20060044030A1 Variation tolerant charge leakage correction circuit for phase locked loops 失效
标题翻译：用于锁相环的变容差电荷泄漏校正电路
公开(公告)号：US20060044030A1
公开(公告)日：2006-03-02
申请号：US10926596
申请日：2004-08-26
申请人： Franklin Baez , David Boerstler , Eskinder Hailu , Kazuhiko Miki
发明人： Franklin Baez , David Boerstler , Eskinder Hailu , Kazuhiko Miki
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L7/095
摘要： The present invention provides for compensation of leakage charge in a PLL. A first plurality and second plurality of charge pumps has a source charge pump and a sink charge pump, and each charge pump has its own switch. A first node is coupled between at least one source charge pump and at least one sink charge pump. A second node coupled between at least one source charge pump and at least one sink charge pump. A PLL filter is coupled to the first node. A dummy filter is coupled to the second node. A first input of a differential mode sensor is coupled to the PLL filter. A second input of a differential mode sensor is coupled to the dummy filter. A first input of a common mode sensor is coupled to the dummy filter. A second input of a common mode sensor coupled to the PLL filter.
摘要翻译：本发明提供了对PLL中的泄漏电荷的补偿。第一多个和第二多个电荷泵具有源电荷泵和吸收电荷泵，并且每个电荷泵具有其自己的开关。第一节点耦合在至少一个源电荷泵和至少一个电荷泵之间。耦合在至少一个源电荷泵和至少一个吸收电荷泵之间的第二节点。 PLL滤波器耦合到第一节点。虚拟滤波器耦合到第二节点。差分模式传感器的第一输入端耦合到PLL滤波器。差模传感器的第二输入端连接到虚拟滤波器。共模传感器的第一输入耦合到虚拟滤波器。耦合到PLL滤波器的共模传感器的第二输入。

124. 发明申请

US20050091620A1 Simplified method for limiting clock pulse width 失效
标题翻译：限制时钟脉冲宽度的简化方法
公开(公告)号：US20050091620A1
公开(公告)日：2005-04-28
申请号：US10692416
申请日：2003-10-23
申请人： Anthony Aipperspach , David Boerstler , Eskinder Hailu
发明人： Anthony Aipperspach , David Boerstler , Eskinder Hailu
IPC分类号： G06F1/04 , G06F9/45 , H03K5/04 , H03K5/156
CPC分类号： G06F1/04 , H03K5/04 , H03K5/1565
摘要： The present invention provides for correcting excessive pulse widths using incremental delays. The pulse width is evaluated through a correction block and leak detector. An acceptable pulse passes through an interconnect directly to the clock output. Unacceptable pulses are sent through a block delay module that incorporates a series of delay sub-blocks that disconnect and reset in accordance with a pre-programmed total delay time. The conditioned clock pulse is resent through a node to the correction block and leak detector where it is reevaluated. If the pulse is acceptable, it is sent to the clock output. If the pulse is found unacceptable, it is recycled again. A high low clock pulse shuttle determines and alters the high or low state of the clock pulse to ensure a correct output to downstream dependent devices.
摘要翻译：本发明提供使用增量延迟来校正过多的脉冲宽度。通过校正块和泄漏检测器来评估脉冲宽度。可接受的脉冲通过互连直接连接到时钟输出。不可接受的脉冲通过块延迟模块发送，该模块延迟模块包含一系列根据预编程的总延迟时间断开和复位的延迟子块。经调节的时钟脉冲通过节点重新发送到校正块和泄漏检测器，在那里它被重新评估。如果脉冲是可接受的，则将其发送到时钟输出。如果发现脉冲不可接受，则再次被再循环。高时钟脉冲穿梭确定并改变时钟脉冲的高或低状态，以确保向下游相关设备输出正确的输出。

125. 发明授权

US08086989B2 Structure for glitchless clock multiplexer optimized for synchronous and asynchronous clocks 有权
标题翻译：针对同步和异步时钟优化的无毛刺时钟复用器的结构
公开(公告)号：US08086989B2
公开(公告)日：2011-12-27
申请号：US12174572
申请日：2008-07-16
申请人： Eskinder Hailu , Takeo Yasuda
发明人： Eskinder Hailu , Takeo Yasuda
IPC分类号： G06F17/50
CPC分类号： G06F17/5059 , G06F2217/84
摘要： A design structure for a circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The design structure comprises a circuit having an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency (period in which no clock pulse appears at the final output of the circuit) from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal.
摘要翻译：用于使用针对同步和异步时钟优化的无毛刺时钟复用器的逻辑器件来切换时钟信号的电路的设计结构。该设计结构包括具有异步时钟组和一个或多个同步时钟组的电路。异步组包括用于异步时钟源的多个高频无毛刺控制（HFGC）块。每个同步组包括用于同步时钟源的多个HFGC块。该电路包括用于从用于异步时钟源的HFGC块和用于同步时钟源的HFGC块接收延迟的输入时钟信号的多路复用器。属于同步组的属于同步组的第一输入时钟信号与属于同一同步组的第二输入时钟信号的开关延迟（在电路的最终输出处没有出现时钟脉冲的周期）是第二输入时钟信号。

126. 发明申请

US20090164957A1 Design Structure for Glitchless Clock Multiplexer Optimized for Synchronous and Asynchronous Clocks 有权
标题翻译：用于同步和异步时钟优化的无毛刺时钟多路复用器的设计结构
公开(公告)号：US20090164957A1
公开(公告)日：2009-06-25
申请号：US12174572
申请日：2008-07-16
申请人： Eskinder Hailu , Takeo Yasuda
发明人： Eskinder Hailu , Takeo Yasuda
IPC分类号： G06F17/50
CPC分类号： G06F17/5059 , G06F2217/84
摘要： A design structure for a circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The design structure comprises a circuit having an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency (period in which no clock pulse appears at the final output of the circuit) from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal.
摘要翻译：用于使用针对同步和异步时钟优化的无毛刺时钟复用器的逻辑器件来切换时钟信号的电路的设计结构。该设计结构包括具有异步时钟组和一个或多个同步时钟组的电路。异步组包括用于异步时钟源的多个高频无毛刺控制（HFGC）块。每个同步组包括用于同步时钟源的多个HFGC块。该电路包括用于从用于异步时钟源的HFGC块和用于同步时钟源的HFGC块接收延迟的输入时钟信号的多路复用器。属于同步组的属于同步组的第一输入时钟信号与属于同一同步组的第二输入时钟信号的开关延迟（在电路的最终输出处没有出现时钟脉冲的周期）是第二输入时钟信号。

127. 发明申请

US20080272820A1 Circuit to Reduce Transient Current Swings During Mode Transitions of High Frequency/High Power Chips 有权
标题翻译：在高频/高功率芯片模式转换期间减少瞬态电流摆幅的电路
公开(公告)号：US20080272820A1
公开(公告)日：2008-11-06
申请号：US12132871
申请日：2008-06-04
申请人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
发明人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
IPC分类号： H03K3/00
CPC分类号： H03K23/662 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.
摘要翻译：提供了一种方法，装置和计算机程序以减少模式转换期间的瞬态电流摆动。传统上，芯片上的瞬态电源电压波动占大部分电源。串联电感和电阻的数量通常最小化，同时在电源电压和地之间增加大的去耦电容。然而，不能实现串联电感和电阻的降低的情况。因此，为了帮助控制瞬态电流摆动，以受控的方式执行时钟频率的降低。

128. 发明申请

US20070043798A1 Random number generator 失效
标题翻译：随机数发生器
公开(公告)号：US20070043798A1
公开(公告)日：2007-02-22
申请号：US11204402
申请日：2005-08-16
申请人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
发明人： David Boerstler , Eskinder Hailu , Harm Hofstee , John Liberty
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H04L9/001 , H04L9/0869
摘要： A random number generator, a method, and a computer program product are provided for producing a random number seed. Each oscillator within an array of oscillators operates at a different frequency. The operating frequencies of each oscillator are not harmonically related, such that no integer multiple exists between the frequencies of any two oscillators. In one embodiment, the outputs of the array of oscillators connect to a multiple input latch. The multiple input latch also receives a sample signal, which is a clock signal. The clock signal samples the outputs of the array of oscillators, and the multiple input latch in conjunction with the random number determination logic (“RNDL”) produces a digital output (0 or 1) for each oscillator within the array. The RNDL uses these digital outputs to create a random number seed.
摘要翻译：提供随机数生成器，方法和计算机程序产品用于产生随机数种子。振荡器阵列内的每个振荡器以不同的频率工作。每个振荡器的工作频率不是谐波相关的，使得在任何两个振荡器的频率之间不存在整数倍。在一个实施例中，振荡器阵列的输出连接到多输入锁存器。多输入锁存器还接收作为时钟信号的采样信号。时钟信号对振荡器阵列的输出采样，并且多输入锁存器与随机数确定逻辑（“RNDL”）一起为阵列内的每个振荡器产生数字输出（0或1）。 RNDL使用这些数字输出创建一个随机数字种子。

129. 发明授权

US07171318B2 PLL filter leakage sensor 失效
标题翻译： PLL滤波器泄漏传感器
公开(公告)号：US07171318B2
公开(公告)日：2007-01-30
申请号：US10870533
申请日：2004-06-17
申请人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki
发明人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki
IPC分类号： G01R19/00
CPC分类号： H03L7/093
摘要： The present invention provides a method, apparatus, and computer program for measuring the current leakage in a Low Pass Filter (LPF) capacitor of a Phased Locked Loop (PLL). As a result of thinner and thinner film capacitors in Complementary Metal-Oxide Semiconductor (CMOS) technology, leakage current, which causes a PLL to drift out of phase lock, has become an increasingly difficult problem. To overcome the leakage current problems, knowing the leakage current of an LPF capacitor is important to implement the correction circuitry. In the present invention, an external interface and a time interface analyzer are used to charge the LPF capacitor and measure the output frequency of the PLL's Voltage Controlled Oscillator. Because of the change in the output frequency, the leakage current can be determined.
摘要翻译：本发明提供一种用于测量相位锁定环（PLL）的低通滤波器（LPF）电容器中的电流泄漏的方法，装置和计算机程序。由于互补金属氧化物半导体（CMOS）技术中薄膜电容器越来越薄，导致PLL漂移出相位锁定的漏电流已经成为越来越难的问题。为了克服漏电流问题，知道LPF电容器的漏电流对于实现校正电路是重要的。在本发明中，使用外部接口和时间接口分析器对LPF电容器充电并测量PLL的压控振荡器的输出频率。由于输出频率的变化，可以确定漏电流。

130. 发明申请

US20060069929A1 Circuit to reduce power supply fluctuations in high frequency/ high power circuits 有权
标题翻译：降低高频/高功率电路电源波动的电路
公开(公告)号：US20060069929A1
公开(公告)日：2006-03-30
申请号：US10955121
申请日：2004-09-30
申请人： David Boerstler , Eskinder Hailu , Mack Riley , Michael Wang
发明人： David Boerstler , Eskinder Hailu , Mack Riley , Michael Wang
IPC分类号： G06F1/26
CPC分类号： G06F1/26
摘要： The present invention provides for a circuit for transitioning clocking speeds. A counter is coupled to the clocking means. A comparator is coupled to an output of the counter. A first divider is coupled to the output of the counter. A processor means is coupled to the output of the first divider, thereby lessening current surges.
摘要翻译：本发明提供了一种用于转换时钟速度的电路。计数器耦合到计时装置。比较器耦合到计数器的输出端。第一分频器耦合到计数器的输出端。处理器装置耦合到第一分频器的输出，从而减小电流浪涌。

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