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111. 发明授权

US5671185A Apparatus for replacing defective cells in a memory device 失效
标题翻译：用于替换存储器件中的有缺陷的单元的装置
公开(公告)号：US5671185A
公开(公告)日：1997-09-23
申请号：US614386
申请日：1996-03-12
申请人： Wei Chen , Tung Chi Chang
发明人： Wei Chen , Tung Chi Chang
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/80 , G11C29/808
摘要： A method and apparatus for effecting repair or replacement of defective circuits in a solid state memory chip includes locating all the spare cells on one block. A circuit for switching redundancy spare cells in place of main wordline cells includes a first portion for providing a first output whenever both inputs are present and a second output at all other times, the first input that is always present and a second input that is present whenever repair is not selected, a second portion having a first input connected to the output of the first portion and a second input that is absent when repair is indicated, the second portion having a first output whenever one of the inputs is present and a second output whenever neither input is present, a third portion connected to the output of the first portion through a circuit that inverts the value of the output from the first portion and a second input that is present when repair is indicated, the third portion producing a first output whenever both inputs are present and a second output at all other times.
摘要翻译：用于对固态存储器芯片中的故障电路进行修复或更换的方法和装置包括将所有备用单元定位在一个块上。用于切换冗余备用单元以代替主字线单元的电路包括：第一部分，用于在两个输入存在时提供第一输出，并且在所有其他时间提供第二输出，总是存在的第一输入和存在的第二输入每当没有选择修复时，具有连接到第一部分的输出的第一输入的第二部分和指示修复时不存在的第二输入，每当输入之一存在时，第二部分具有第一输出，而第二部分存在第二输入输出，每当输入都不存在时，第三部分通过反转来自第一部分的输出的值的电路和在指示修复时存在的第二输入连接到第一部分的输出，第三部分产生第一部分每当两个输入都存在时输出，而在其他时间输出第二个输出。

112. 发明授权

US5671169A Apparatus for two-dimensional inverse discrete cosine transform 失效
标题翻译：二维逆离散余弦变换装置
公开(公告)号：US5671169A
公开(公告)日：1997-09-23
申请号：US494597
申请日：1995-06-23
申请人： Po-Chuan Huang
发明人： Po-Chuan Huang
IPC分类号： G06F17/14
CPC分类号： G06F17/147
摘要： An apparatus for real time 2-D IDCT comprises a rate buffer, a pair of multiplexers, a plurality of registers, a plurality of parameter extractors, a plurality of accumulators, a plurality of summing elements, a pair of truncators, a transpose buffer and an inverse rate buffer. In the present invention, data input rate of the rate buffer and output rate of the inverse rate buffer are a first rate, while the transform process, which is carried out between the rate buffer and the inverse rate buffer, is at a second rate. Moreover, a distributed arithmetic structure is utilized in the invention to decrease the circuit complexity and increase the operating efficiency. Therefore, real time 2-D IDCT can be achieved by the apparatus of the present invention.
摘要翻译：一种用于实时2-D IDCT的装置包括速率缓冲器，一对多路复用器，多个寄存器，多个参数提取器，多个累加器，多个求和元件，一对截断器，转置缓冲器和反向速率缓冲器。在本发明中，速率缓冲器的数据输入速率和反向速率缓冲器的输出速率是第一速率，而在速率缓冲器和反向速率缓冲器之间执行的变换处理是第二速率。此外，在本发明中利用分布式算术结构来降低电路复杂度并提高其工作效率。因此，可以通过本发明的装置实现实时2-D IDCT。

113. 发明授权

US5668029A Process for fabricating multi-level read-only memory device 失效
标题翻译：制造多级只读存储器件的过程
公开(公告)号：US5668029A
公开(公告)日：1997-09-16
申请号：US642941
申请日：1996-05-06
申请人： Heng-Sheng Huang , Fong-Chun Lee
发明人： Heng-Sheng Huang , Fong-Chun Lee
IPC分类号： H01L21/8246 , H01L21/265
CPC分类号： H01L27/11233
摘要： A process for fabricating multi-level semiconductor ROM devices is disclosed. Each memory cell of the ROM device can be programmed to any of three possible conduction states including full-conduction, half-conduction and no-conduction. The fabrication process begins with a semiconductor silicon substrate. Buried bit and word lines are formed in the substrate. A photomask is then formed to correspond to code to be programmed into the ROM device. The photomask, when properly aligned over the ROM device, contains portions that fully cover the entire channel region of a cell to be programmed for full conduction, portions that partially cover the channel regions of cells that are to be programmed for half-conduction, and portions that do not cover at all the channel regions of cells to be programmed for no-conduction. Then ions are implanted with the photomask in place. The ions transform the regions not covered or partially covered by the photomask. In use, three levels of conduction current may then be sensed when the ROM device is accessed to represent three data levels.
摘要翻译：公开了一种用于制造多电平半导体ROM器件的工艺。可以将ROM器件的每个存储单元编程为包括全导通，半导通和无导通的三种可能的导通状态中的任何一种。制造工艺从半导体硅衬底开始。在衬底中形成埋置的位和字线。然后形成光掩模以对应于要编程到ROM设备中的代码。光掩模在ROM器件上正确对准时，包含完全覆盖要被编程为完全传导的单元的整个通道区域的部分，部分地覆盖要被编程为半导体的单元的沟道区域的部分，以及部分不覆盖要编程为不导通的单元的所有通道区域。然后将离子植入光掩模就位。离子转换未覆盖或部分被光掩模覆盖的区域。在使用中，当ROM器件被访问以表示三个数据电平时，可以感测到三个级别的导通电流。

114. 发明授权

US5665632A Stress relaxation in dielectric before metalization 失效
标题翻译：金属化前电介质的应力松弛
公开(公告)号：US5665632A
公开(公告)日：1997-09-09
申请号：US608071
申请日：1996-02-28
申请人： Water Lur , Edward Houn
发明人： Water Lur , Edward Houn
IPC分类号： H01L21/308 , H01L21/311 , H01L21/336 , H01L21/762 , H01L21/763 , H01L21/31 , H01L21/764
CPC分类号： H01L29/6659 , H01L21/3086 , H01L21/31144 , H01L21/76229 , H01L21/763 , H01L29/6656 , Y10S148/073 , Y10S257/90 , Y10S438/938
摘要： A new method of trench isolation incorporating thermal stress releasing voids is described. Two sets of narrow trenches are etched into the silicon substrate not covered by a photoresist mask wherein the second set of trenches alternate with the first set of trenches. The first set of trenches is filled with an insulating layer. A second insulating layer is deposited over the surface of the substrate and within the second set of trenches wherein said insulating layer has step coverage such that voids are formed and are completely enclosed within the second set of trenches completing the thermal stress releasing device isolation of the integrated circuit. The method of forming thermal stress released polysilicon gate spacers in an integrated circuit is described. Polysilicon gate electrodes are formed on the surface of the semiconductor substrate. Sucessive sidewalls are formed on the gate electrodes of thin silicon dioxide, silicon nitride, and silicon dioxide. The silicon nitride spacers are removed leaving trenches between the thin silicon dioxide sidewalls and the silicon dioxide spacers. A thin insulating material is deposited over the surface of the gate electrodes and the sidewalls with a step coverage such that the trenches between the thin oxidation and the silicon dioxide spacers are not filled by the thin insulating layer but are covered by the thin insulating layer leaving voids which complete the thermal stress released polysilicon gate spacer formation in the fabrication of an integrated circuit.
摘要翻译：描述了一种结合热应力释放空隙的新型沟槽隔离方法。将两组窄沟槽蚀刻到未被光致抗蚀剂掩模覆盖的硅衬底中，其中第二组沟槽与第一组沟槽交替。第一组沟槽填充有绝缘层。第二绝缘层沉积在衬底的表面上并在第二组沟槽内，其中所述绝缘层具有阶梯覆盖，使得形成空隙并完全封闭在第二组沟槽内，从而完成热应力释放装置的隔离集成电路。描述了在集成电路中形成热应力释放多晶硅栅极间隔物的方法。多晶硅栅电极形成在半导体衬底的表面上。在薄二氧化硅，氮化硅和二氧化硅的栅电极上形成过多的侧壁。去除氮化硅间隔物，留下薄二氧化硅侧壁和二氧化硅间隔物之间的沟槽。薄的绝缘材料沉积在栅电极和侧壁的表面上，具有台阶覆盖，使得薄氧化物和二氧化硅间隔物之间的沟槽不被薄绝缘层填充，但被薄绝缘层覆盖，离开完成热应力的空隙在集成电路的制造中释放多晶硅栅极间隔物的形成。

115. 发明授权

US5665624A Method for fabricating trench/stacked capacitors on DRAM cells with increased capacitance 失效
标题翻译：在具有增加的电容的DRAM单元上制造沟槽/层叠电容器的方法
公开(公告)号：US5665624A
公开(公告)日：1997-09-09
申请号：US735221
申请日：1996-10-22
申请人： Gary Hong
发明人： Gary Hong
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10835
摘要： A method is described for making an array of dynamic random access memory (DRAM) cells having a trench/stacked capacitor within each cell. The method involves forming trenches in the silicon substrate at the capacitor node contact areas of the DRAM cells, and using liquid phase deposition (LPD) of silicon oxide in the trenches to form oxide plugs that extend upward into the openings in the photoresist mask used to etch the trenches. After removing the photoresist, polysilicon sidewall spacers are formed on the LPD oxide plugs. The sidewall spacers become part of the stacked capacitor structures. Another patterned polysilicon layer is used to form the array of storage-node electrodes for the stacked capacitors, and also serve as the storage-node electrodes for the trench capacitors. Conventional methods are used to complete the array of trench/stacked capacitors by depositing an interelectrode dielectric layer and then forming the polysilicon top electrodes.
摘要翻译：描述了一种制造在每个单元内具有沟槽/层叠电容器的动态随机存取存储器（DRAM）单元阵列的方法。该方法包括在DRAM单元的电容器节点接触区域处的硅衬底中形成沟槽，并且在沟槽中使用氧化硅的液相沉积（LPD）形成向上延伸到光致抗蚀剂掩模中的开口中的氧化物塞，其用于蚀刻沟槽。在去除光致抗蚀剂之后，在LPD氧化物塞上形成多晶硅侧壁间隔物。侧壁间隔物成为叠层电容器结构的一部分。使用另一个图案化多晶硅层形成堆叠电容器的存储节点电极阵列，并且还用作沟槽电容器的存储节点电极。使用常规方法通过沉积电极间电介质层然后形成多晶硅顶电极来完成沟槽/层叠电容器阵列。

116. 发明授权

US5650780A Decoding for tri-state read-only memory 失效
标题翻译：解码三态只读存储器
公开(公告)号：US5650780A
公开(公告)日：1997-07-22
申请号：US426903
申请日：1995-04-21
申请人： Fong-Chun Lee
发明人： Fong-Chun Lee
IPC分类号： G11C11/56 , H03M5/16
CPC分类号： G11C11/5692 , G11C11/56 , H03M5/16 , G11C7/1006
摘要： A decoding method for tri-state read-only memory is disclosed herein. The cells of the tri-state memory are read the storage bits of all cells are combined to form a storage code. Each bit represents one of a first state, a second state and a third state. The storage code is first decoded to convert the storage code into an intermediate code. The intermediate code includes a plurality of conversion codes, each of which is one of a first code, a second code, and a third code corresponding respectively to the first, second, and third states. The intermediate code is further decoded into the binary output code. The resulting binary code has a greater number of bits than its corresponding storage code. Thus, the read-only memory, in accordance with the present invention, can store more than one bit of data in a single memory cell.
摘要翻译：本文公开了三态只读存储器的解码方法。读取三态存储器的单元，将所有单元的存储位组合以形成存储代码。每个位表示第一状态，第二状态和第三状态之一。存储代码首先被解码以将存储代码转换成中间代码。中间代码包括多个转换代码，每个转换代码分别是对应于第一，第二和第三状态的第一代码，第二代码和第三代码之一。中间代码进一步被解码成二进制输出代码。所得到的二进制代码具有比其对应的存储代码更多的位数。因此，根据本发明的只读存储器可以在单个存储器单元中存储多于一个位的数据。

117. 发明授权

US5634029A Apparatus for interchanging floppy diskette drive assignments 失效
标题翻译：用于交换软盘驱动器分配的装置
公开(公告)号：US5634029A
公开(公告)日：1997-05-27
申请号：US529733
申请日：1995-09-18
申请人： Chih-Hsien Chen
发明人： Chih-Hsien Chen
IPC分类号： G06F13/42 , H01H9/00
CPC分类号： G06F13/4226 , Y10T307/839
摘要： A floppy diskette drive assignment interchanging apparatus for interchanging the drive letter assignments in a computer system is disclosed. The floppy diskette drives have a drive data cable that includes a number of data lines. The interchanging apparatus comprises an interchange control logic and an assignment interchange logic. The interchange control logic generates an optional interchange control signal, the interchange control signal signifies the requirement for interchange when it is in a first logic state, and signifies the requirement of maintaining no interchange when it is in a second logic state. The assignment interchange logic has a set of inputs connected to each of the data lines among the drive cable data lines that require interchanging, and has a set of outputs for outputting the set of inputs with an output assignment of either a forward or reverse order determined by the active and inactive status of the interchange control signal.
摘要翻译：公开了一种用于交换计算机系统中的驱动器号分配的软盘驱动器分配交换装置。软盘驱动器具有包含多条数据线的驱动器数据电缆。交换装置包括交换控制逻辑和分配交换逻辑。交换控制逻辑产生可选择的交换控制信号，当交换控制信号处于第一逻辑状态时，交换控制信号表示交换的要求，并且表示在处于第二逻辑状态时不保持互换的要求。分配交换逻辑具有连接到需要交换的驱动电缆数据线中的每条数据线的一组输入，并且具有一组输出，用于输出该组输入，其中输出分配是正向或反向顺序确定的通过交换控制信号的主动和非活动状态。

118. 发明授权

US5631486A Read-only-memory having both bipolar and channel transistors 失效
标题翻译：具有双极和沟道晶体管的只读存储器
公开(公告)号：US5631486A
公开(公告)日：1997-05-20
申请号：US532068
申请日：1995-09-22
申请人： Chen-Chung Hsu
发明人： Chen-Chung Hsu
IPC分类号： H01L27/112 , H01L29/06
CPC分类号： H01L27/112
摘要： A structure for a read-only-memory (ROM) having both bipolar and channel transistors as memory cells to achieve efficient space utilization and higher density of ROM elements. The channel transistors include bit lines and word lines, with a threshold voltage at about 0.7 V. By implanting impurities into predetermined channel regions, memory cells become conductive or non-conductive. Bipolar transistors are formed in predetermined intersections of bit lines and word lines with a threshold voltage of about 3 V to 5 V, which can be treated as conductive memory cells that conduct current under 5 V operating voltage. Intersections of bit lines and word lines without bipolar transistors formed therein can be treated as non-conductive memory cells.
摘要翻译：具有作为存储单元的双极和沟道晶体管的只读存储器（ROM）的结构，以实现有效的空间利用和较高密度的ROM元件。沟道晶体管包括位线和字线，阈值电压约为0.7V。通过将杂质注入预定的沟道区域，存储器单元变成导电或非导电的。双极晶体管形成在具有约3V至5V的阈值电压的位线和字线的预定交点中，其可以被视为在5V工作电压下传导电流的导电存储器单元。位于其中形成双极晶体管的位线和字线的交点可被视为非导电存储单元。

119. 发明授权

US5627106A Trench method for three dimensional chip connecting during IC fabrication 失效
标题翻译： IC制造期间三维芯片连接的沟槽法
公开(公告)号：US5627106A
公开(公告)日：1997-05-06
申请号：US239281
申请日：1994-05-06
申请人： Chen-Chung Hsu
发明人： Chen-Chung Hsu
IPC分类号： H01L21/768 , H01L21/98 , H01L25/065 , H01L21/44
CPC分类号： H01L25/50 , H01L21/76898 , H01L25/0657 , H01L2224/13009 , H01L2224/8114 , H01L2225/06513 , H01L2225/06541
摘要： A new method of connecting three-dimensional integrated circuit chips using trench technology is described. Semiconductor device structures are provided in and on the top side of a semiconductor substrate of a first and a second three-dimensional integrated circuit chip. Deep trenches are etched into the first semiconductor substrate. A conductive material is deposited into the trenches. An insulating material is deposited over the surface of the substrate, polished and planarized. The bottom side of the first semiconductor substrate is ground, polished, and selectively etched so that the deep trenches form protrusions from the bottom surface. A passivation layer and a polyimide layer are deposited on the bottom surface of the first semiconductor substrate and etched away around the protrusions. A passivation layer and a polyimide layer are deposited over the top surface of the second semiconductor substrate. Connection windows are etched through the two layers to the top conducting surface of the second semiconductor substrate. The first and second integrated circuits are aligned so that the protrusions on the bottom surface of the first integrated circuit chip fit into the connection windows in the top surface of the second integrated circuit chip. The polyimide layer on the bottom surface of the first integrated circuit contacts the polyimide layer on the top surface of the second integrated circuit completing the connection between the two chips.
摘要翻译：描述了使用沟槽技术连接三维集成电路芯片的新方法。半导体器件结构设置在第一和第二三维集成电路芯片的半导体衬底的顶侧中和上侧。深沟槽被蚀刻到第一半导体衬底中。导电材料沉积到沟槽中。绝缘材料沉积在基板的表面上，被抛光和平坦化。第一半导体衬底的底侧被研磨，抛光和选择性蚀刻，使得深沟槽从底表面形成突起。钝化层和聚酰亚胺层沉积在第一半导体衬底的底表面上，并围绕突起蚀刻掉。钝化层和聚酰亚胺层沉积在第二半导体衬底的顶表面上。连接窗口通过两层被蚀刻到第二半导体衬底的顶部导电表面。第一集成电路和第二集成电路对准，使得第一集成电路芯片的底表面上的突起嵌入第二集成电路芯片的顶表面中的连接窗口。第一集成电路的底表面上的聚酰亚胺层与第二集成电路的顶表面上的聚酰亚胺层接触，从而完成两芯片之间的连接。

120. 发明授权

US5624857A Process for fabricating double well regions in semiconductor devices 失效
标题翻译：在半导体器件中制造双阱区的工艺
公开(公告)号：US5624857A
公开(公告)日：1997-04-29
申请号：US422298
申请日：1995-04-14
申请人： Sheng-Hsing Yang
发明人： Sheng-Hsing Yang
IPC分类号： H01L21/8238 , H01L21/761
CPC分类号： H01L21/823892
摘要： A process for fabricating double well regions for a semiconductor device having a first well region of a first type and a second well region of a second type on the substrate is disclosed. The process comprises the steps of first implanting impurities of the first type into the substrate. Then a shielding layer covering the location designated for the first well region of the first type on the substrate is formed. Impurities of the second type are then implanted into the substrate at locations not covered by the shielding layer and designated for the formation of the second well region of the second type. Finally, the impurities of both the first and the second type are driven into a designated depth of the substrate by a heating process to form the first well region of the first type and the second well region of the second type.
摘要翻译：公开了一种在衬底上制造具有第一类型的第一阱区和第二类型的第二阱区的半导体器件的双阱区的工艺。该方法包括首先将第一类型的杂质注入衬底的步骤。然后形成覆盖基板上第一类型的第一阱区域的位置的屏蔽层。然后将第二类型的杂质注入到未被屏蔽层覆盖的位置并被指定用于形成第二类型的第二阱区的基板中。最后，通过加热工艺将第一和第二类型的杂质驱动到衬底的指定深度，以形成第二类型的第一阱区域和第二类型的第二阱区域。

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