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111. 发明授权

US07629024B2 Methods of forming particle-containing materials 失效
标题翻译：形成含颗粒材料的方法
公开(公告)号：US07629024B2
公开(公告)日：2009-12-08
申请号：US11486522
申请日：2006-07-13
申请人： Garo J. Derderian , Gurtej S. Sandhu
发明人： Garo J. Derderian , Gurtej S. Sandhu
IPC分类号： B05D1/12 , H01L21/471
CPC分类号： H01L21/76838 , C23C16/45525 , C23C16/45555 , H01L21/02126 , H01L21/02164 , H01L21/0226 , H01L21/0228 , H01L21/288 , H01L21/3141 , H01L21/3146 , H01L21/31608 , H01L21/31633 , H01L21/76829 , H01L21/76837 , Y10S438/962 , Y10S438/964 , Y10T428/12493 , Y10T428/12528 , Y10T428/12576 , Y10T428/12806 , Y10T428/1284
摘要： The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semiconductor substrate, particles are adhered to the first monolayer, and a second monolayer is formed over the particles. Another aspect of the invention includes a construction containing a semiconductor substrate and a particle-impregnated conductive material over at least a portion of the semiconductor substrate. The particle-impregnated conductive material can include tungsten-containing particles within a layer which includes tantalum or tungsten.
摘要翻译：本发明包括形成含颗粒材料的方法，还包括包含含颗粒的材料的半导体结构。本发明的一个方面包括一种方法，其中在半导体衬底的至少一部分上形成第一单层，颗粒粘附到第一单层，并且在颗粒上方形成第二单层。本发明的另一方面包括在半导体衬底的至少一部分上包含半导体衬底和含有颗粒的导电材料的结构。颗粒浸渍的导电材料可以包括在包括钽或钨的层内的含钨颗粒。

112. 发明申请

US20090263962A1 NON-VOLATILE MEMORY CELL DEVICE AND METHODS 有权
标题翻译：非易失性记忆细胞装置及方法
公开(公告)号：US20090263962A1
公开(公告)日：2009-10-22
申请号：US12496437
申请日：2009-07-01
申请人： Gurtej S. Sandhu , Kirk D. Prall
发明人： Gurtej S. Sandhu , Kirk D. Prall
IPC分类号： H01L21/28 , H01L21/311
CPC分类号： H01L29/7881 , B82Y10/00 , G11C16/0408 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/513
摘要： A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming a second dielectric layer over the nanodots, where the second dielectric layer encases the nanodots. In addition, an intergate dielectric layer is formed over the second dielectric layer. To form sidewalls of the memory cell, a portion of the intergate dielectric layer and a portion of the second dielectric layer are removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the second dielectric layer and the nanodots can be removed with an isotropic etch selective to the second dielectric layer.
摘要翻译：一种制造存储单元的方法，包括在第一介电层上形成纳米点，并在纳米点上形成第二介电层，其中第二介电层包裹纳米点。此外，在第二介电层上形成隔间电介质层。为了形成存储器单元的侧壁，间隔电介质层的一部分和第二电介质层的一部分用干蚀刻去除，其中侧壁包括已经沉积纳米点的位置。在侧壁上形成间隔层以覆盖已经沉积纳米点的位置，并且可以用对第二介电层选择性的各向同性蚀刻去除第二介电层和纳米点的剩余部分。

113. 发明授权

US07598021B2 High resolution printing technique 失效
标题翻译：高分辨率打印技术
公开(公告)号：US07598021B2
公开(公告)日：2009-10-06
申请号：US11252465
申请日：2005-10-17
申请人： Gurtej S. Sandhu
发明人： Gurtej S. Sandhu
IPC分类号： G03F7/20
CPC分类号： H01L21/3088 , B82Y10/00 , G03F7/70383 , G11B9/1436 , G11B9/149 , G11B2005/0021 , H01L21/0337 , H01L21/3086
摘要： A pattern having exceptionally small features is printed on a partially fabricated integrated circuit during integrated circuit fabrication. The pattern is printed using an array of probes, each probe having: 1) a photocatalytic nanodot at its tip; and 2) an individually controlled light source. The surface of the partially fabricated integrated circuit comprises a photochemically active species. The active species undergoes a chemical change when contacted by the nanodot, when the nanodot is illuminated by light. To print a pattern, each probe raster-scans its associated nanodot across the surface of the partially fabricated integrated circuit. When the nanodot reaches a desired location, the nanodot is illuminated by the light source, catalyzing a change in the reactive species and, thus, printing at that location. Subsequently, reacted or unreacted species are selectively removed, thereby forming a mask pattern over the partially fabricated integrated circuit. The minimum size of the features in the pattern is determined by the size of the nanodot and can be very small, e.g., having critical dimensions of about 20 nm or less.
摘要翻译：在集成电路制造期间，在部分制造的集成电路上印刷具有特殊小特征的图案。使用探针阵列打印图案，每个探针具有：1）在其尖端处的光催化纳米点; 和2）单独控制的光源。部分制造的集成电路的表面包括光化学活性物质。当纳米点被光照射时，活性物质与纳米点接触时发生化学变化。为了打印图案，每个探针光栅扫描其部分制造的集成电路的表面上的相关联的纳米点。当纳米点达到所需位置时，纳米点由光源照射，催化反应物种的变化，从而在该位置进行印刷。随后，选择性地除去反应或未反应的物质，从而在部分制造的集成电路上形成掩模图案。图案中的特征的最小尺寸由纳米点的尺寸确定，并且可以非常小，例如具有约20nm或更小的临界尺寸。

114. 发明授权

US07576441B2 Boron-doped amorphous carbon film for use as a hard etch mask during the formation of a semiconductor device 失效
标题翻译：在半导体器件形成期间用作硬蚀刻掩模的硼掺杂非晶碳膜
公开(公告)号：US07576441B2
公开(公告)日：2009-08-18
申请号：US11214367
申请日：2005-08-29
申请人： Zhiping Yin , Gurtej S. Sandhu
发明人： Zhiping Yin , Gurtej S. Sandhu
IPC分类号： H01L23/544
CPC分类号： H01L21/02115 , H01L21/02274 , H01L21/0332 , H01L21/28088 , H01L21/28123 , H01L21/31133 , H01L21/31144 , H01L21/312 , H01L21/32139 , H01L21/76802 , H01L27/10817 , H01L27/10852 , H01L28/84 , H01L28/90
摘要： A hard mask comprising boron-doped amorphous carbon, and a method for forming the hard mask, provides improved resistance to etches of a variety of materials compared with previous amorphous carbon hard mask layers.
摘要翻译：包含硼掺杂的无定形碳的硬掩模和形成硬掩模的方法与先前的无定形碳硬掩模层相比提供了改进的各种材料的蚀刻耐蚀性。

115. 发明授权

US07572710B2 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects 失效
标题翻译：向源极/漏极区形成导电接触的方法以及形成局部互连的方法
公开(公告)号：US07572710B2
公开(公告)日：2009-08-11
申请号：US11525707
申请日：2006-09-21
申请人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
发明人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
IPC分类号： H01L21/338 , H01L21/337 , H01L21/8238 , H01L21/8234 , H01L21/8242 , H01L21/8222 , H01L21/20 , H01L21/4763
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成对场效应晶体管的源极/漏极区的导电接触的方法，以及形成局部互连的方法。在一个实施方案中，形成到场效应晶体管的源/漏区的导电接触的方法包括在晶体管栅极和场效应晶体管的沟道区之间提供栅介质材料。至少一些栅极电介质材料延伸以在场效应晶体管的至少一个源极/漏极区域上接收。接收在一个源极/漏极区域上的栅极电介质材料暴露于有效地将其从电绝缘转变为导电并与一个源极/漏极区域导电接触的条件。考虑了其他方面和实现。

116. 发明授权

US07566907B2 Thin film transistors and semiconductor constructions 失效
标题翻译：薄膜晶体管和半导体结构
公开(公告)号：US07566907B2
公开(公告)日：2009-07-28
申请号：US12135761
申请日：2008-06-09
申请人： Gurtej S. Sandhu , Shubneesh Batra , Pierre C. Fazan
发明人： Gurtej S. Sandhu , Shubneesh Batra , Pierre C. Fazan
IPC分类号： H01L21/00
CPC分类号： H01L29/78678 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/6675 , H01L29/66757 , H01L29/66765 , H01L29/78672 , H01L29/78675
摘要： A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.
摘要翻译：相对于衬底形成薄膜晶体管的方法包括：a）在衬底上提供多晶材料的薄膜晶体管层，所述多晶材料包括晶界; b）在多晶薄膜层附近提供含氟层; c）在一段温度和一段时间内退火含氟层，所述时间段有效地将氟从含氟层驱动到多晶薄膜层中，并且在晶界内引入氟以钝化所述晶界; 以及d）提供与所述薄膜晶体管层可操作地相邻的晶体管栅极。薄膜晶体管可以被制造为底部门控或顶部门控。可以在薄膜晶体管层和含氟层之间设置缓冲层，缓冲层在退火期间从含氟层透过氟。优选地，退火温度足够高以将氟从含氟层驱动到多晶薄膜层中并且在晶界内引入氟以使所述晶界钝化，但是足够低以防止含氟层与多晶薄膜层。

117. 发明授权

US07550848B2 Semiconductor constructions comprising particle-containing materials 失效
标题翻译：包含含颗粒材料的半导体结构
公开(公告)号：US07550848B2
公开(公告)日：2009-06-23
申请号：US11400613
申请日：2006-04-06
申请人： Garo J. Derderian , Gurtej S. Sandhu
发明人： Garo J. Derderian , Gurtej S. Sandhu
IPC分类号： H01L23/48
CPC分类号： H01L21/76838 , C23C16/45525 , C23C16/45555 , H01L21/02126 , H01L21/02164 , H01L21/0226 , H01L21/0228 , H01L21/288 , H01L21/3141 , H01L21/3146 , H01L21/31608 , H01L21/31633 , H01L21/76829 , H01L21/76837 , Y10S438/962 , Y10S438/964 , Y10T428/12493 , Y10T428/12528 , Y10T428/12576 , Y10T428/12806 , Y10T428/1284
摘要： The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semiconductor substrate, particles are adhered to the first monolayer, and a second monolayer is formed over the particles. Another aspect of the invention includes a construction containing a semiconductor substrate and a particle-impregnated conductive material over at least a portion of the semiconductor substrate. The particle-impregnated conductive material can include tungsten-containing particles within a layer which includes tantalum or tungsten.
摘要翻译：本发明包括形成含颗粒材料的方法，还包括包含含颗粒的材料的半导体结构。本发明的一个方面包括一种方法，其中在半导体衬底的至少一部分上形成第一单层，颗粒粘附到第一单层，并且在颗粒上方形成第二单层。本发明的另一方面包括在半导体衬底的至少一部分上包含半导体衬底和含有颗粒的导电材料的结构。颗粒浸渍的导电材料可以包括在包括钽或钨的层内的含钨颗粒。

118. 发明授权

US07550345B2 Methods of forming hafnium-containing materials 有权
标题翻译：形成含铪材料的方法
公开(公告)号：US07550345B2
公开(公告)日：2009-06-23
申请号：US11485593
申请日：2006-07-11
申请人： Cem Basceri , F. Daniel Gealy , Gurtej S. Sandhu
发明人： Cem Basceri , F. Daniel Gealy , Gurtej S. Sandhu
IPC分类号： H01L21/20
CPC分类号： H01G4/33 , H01G4/1209 , H01G4/1272 , H01L21/31645 , H01L27/10852 , H01L28/60 , H01L28/65 , H01L28/90 , H01L28/91 , H01L29/7833
摘要： The invention includes methods of forming hafnium-containing materials, such as, for example, hafnium oxide. In one aspect, a semiconductor substrate is provided, and first reaction conditions are utilized to form hafnium-containing seed material in a desired crystalline phase and orientation over the substrate. Subsequently, second reaction conditions are utilized to grow second hafnium-containing material over the seed material. The second hafnium-containing material is in a crystalline phase and/or orientation different from the crystalline phase and orientation of the hafnium-containing seed material. The second hafnium-containing material can be, for example, in an amorphous phase. The seed material is then utilized to induce a desired crystalline phase and orientation in the second hafnium-containing material. The invention also includes capacitor constructions utilizing hafnium-containing materials, and circuit assemblies comprising the capacitor constructions.
摘要翻译：本发明包括形成含铪材料的方法，例如氧化铪。在一个方面，提供了半导体衬底，并且利用第一反应条件来形成在衬底上所需的结晶相和取向的含铪种子材料。随后，利用第二反应条件在种子材料上生长第二含铪材料。第二含铪材料处于与含铪种子材料的结晶相和取向不同的结晶相和/或取向。第二含铪材料可以是例如非晶相。然后将种子材料用于在第二含铪材料中诱导所需的结晶相和取向。本发明还包括使用含铪材料的电容器结构和包括电容器结构的电路组件。

119. 发明申请

US20090114246A1 Methods For Treating Surfaces 失效
标题翻译：治疗表面的方法
公开(公告)号：US20090114246A1
公开(公告)日：2009-05-07
申请号：US11933770
申请日：2007-11-01
申请人： Nishant Sinha , Gurtej S. Sandhu
发明人： Nishant Sinha , Gurtej S. Sandhu
IPC分类号： B08B6/00 , B08B3/00
CPC分类号： B08B3/10 , B08B7/02 , B24C3/322 , B24C7/0007 , H01L21/02052 , H01L21/02057 , H01L21/67051
摘要： Some embodiments include methods for treating surfaces. Beads and/or other insolubles may be dispersed within a liquid carrier to form a dispersion. A transfer layer may be formed across a surface. The dispersion may be directed toward the transfer layer, and the insolubles may impact the transfer layer. The impacting may generate force in the transfer layer, and such force may be transferred through the transfer layer to the surface. The surface may be a surface of a semiconductor substrate, and the force may be utilized to sweep contaminants from the semiconductor substrate surface. The transfer layer may be a liquid, and in some embodiments may be a cleaning solution.
摘要翻译：一些实施方案包括用于处理表面的方法。珠和/或其他不溶物可以分散在液体载体中以形成分散体。可以跨越表面形成转印层。分散体可以指向转移层，并且不溶物可能影响转移层。冲击可能在转移层中产生力，并且这种力可以通过转移层转移到表面。表面可以是半导体衬底的表面，并且该力可用于从半导体衬底表面扫除污染物。转移层可以是液体，并且在一些实施方案中可以是清洁溶液。

120. 发明授权

US07498057B2 Deposition methods 失效
标题翻译：沉积方法
公开(公告)号：US07498057B2
公开(公告)日：2009-03-03
申请号：US11075017
申请日：2005-03-08
申请人： Demetrius Sarigiannis , Garo J. Derderian , Cem Basceri , Gurtej S. Sandhu , F. Daniel Gealy , Chris M. Carlson
发明人： Demetrius Sarigiannis , Garo J. Derderian , Cem Basceri , Gurtej S. Sandhu , F. Daniel Gealy , Chris M. Carlson
IPC分类号： C23C16/04
CPC分类号： C23C16/45519 , C23C16/4401 , C23C16/455
摘要： A deposition method includes positioning a substrate within a deposition chamber defined at least in part by chamber walls. At least one of the chamber walls comprises a chamber surface having a plurality of purge gas inlets to the chamber therein. A process gas is provided over the substrate effective to deposit a layer onto the substrate. During such providing, a material adheres to the chamber surface. Reactive purge gas is emitted to the deposition chamber from the purge gas inlets effective to form a reactive gas curtain over the chamber surface and away from the substrate, with such reactive gas reacting with such adhering material. Further implementations are contemplated.
摘要翻译：沉积方法包括将基板定位在至少部分地由室壁限定的沉积室内。所述室壁中的至少一个包括腔室表面，其中具有多个吹扫气体入口。在衬底上设置工艺气体，有效地将层沉积到衬底上。在这种提供过程中，材料粘附到室表面。反应性净化气体从吹扫气体入口排出到沉积室，有效地在室表面上形成反应性气体帘幕并远离衬底，这种反应性气体与这种粘附材料反应。考虑进一步的实现。

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