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101. 发明授权

US06479346B1 Semiconductor memory device and fabrication method thereof 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06479346B1
公开(公告)日：2002-11-12
申请号：US09544214
申请日：2000-04-07
申请人： Sang-Bai Yi , Jae-Min Yu , Sung-Chul Lee
发明人： Sang-Bai Yi , Jae-Min Yu , Sung-Chul Lee
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11539 , Y10S257/903
摘要： In a semiconductor memory device including memory cells and a peripheral circuit unit, a memory cell has a first gate structure formed on a semiconductor substrate; a first impurity region of a first conductive type formed in the substrate on a first side of the gate structure; and a second impurity region formed in the substrate on a second side of the gate structure, the second impurity region including: a third impurity region of the first conductive type, a fourth impurity region of the first conductive type between the third impurity region and the second side of the gate structure, and a halo ion region of a second conductive type formed adjacent to the fourth impurity region.
摘要翻译：在包括存储单元和外围电路单元的半导体存储器件中，存储单元具有形成在半导体衬底上的第一栅极结构; 第一导电类型的第一杂质区域形成在栅极结构的第一侧上的衬底中; 以及形成在所述栅极结构的第二侧上的所述衬底中的第二杂质区域，所述第二杂质区域包括：第一导电类型的第三杂质区域，第三杂质区域和第三杂质区域之间的第一导电类型的第四杂质区域，栅极结构的第二侧和与第四杂质区相邻形成的第二导电类型的晕圈离子区。

102. 发明申请

US20020045316A1 METHOD OF MANUFACTURING AN INTEGRATED SEMICONDUCTOR DEVICE HAVING A NONVOLATILE FLOATING GATE MEMIRY, AND RELATED INTEGRATED DEVICE 有权
标题翻译：制造具有非挥发性浮选机组的集成半导体器件的制造方法及相关的集成器件
公开(公告)号：US20020045316A1
公开(公告)日：2002-04-18
申请号：US09415021
申请日：1999-10-07
发明人： LIVIO BALDI , ALFONSO MAURELLI
IPC分类号： H01L021/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11539 , H01L27/11546
摘要： A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor. The method includes growing a first gate oxide layer over a silicon substrate, depositing a first polysilicon layer over the first gate oxide layer, selectively etching and removing the first polysilicon layer in order to define the floating gate of the memory cell, introducing dopant in order to obtain source and drain regions of the memory cell, depositing a dielectric layer, selectively etching and removing the dielectric layer and the first polysilicon layer in a region wherein the logic transistor will be formed, depositing a second polysilicon layer, selectively etching and removing the second polysilicon layer in order to define the gate of the logic transistor and the control gate of the memory cell. Between selectively etching the dielectric and depositing a second polysilicon layer, a first sub-step of removing the first gate oxide layer in the region for the logic transistor, and a second sub-step of growing a second oxide gate layer over the region, the second gate oxide layer having a different thickness than the first gate oxide layer.
摘要翻译：一种制造具有至少一个非易失性浮动栅极存储单元和至少一个逻辑晶体管的集成半导体器件的方法。该方法包括在硅衬底上生长第一栅极氧化层，在第一栅极氧化物层上沉积第一多晶硅层，选择性地蚀刻和去除第一多晶硅层，以便限定存储单元的浮置栅极，按顺序引入掺杂剂为了获得存储单元的源极和漏极区域，沉积介电层，在将形成逻辑晶体管的区域中选择性地蚀刻和去除电介质层和第一多晶硅层，沉积第二多晶硅层，选择性地蚀刻和去除第二多晶硅层，以便限定逻辑晶体管的栅极和存储器单元的控制栅极。在选择性地蚀刻电介质并沉积第二多晶硅层之间，去除用于逻辑晶体管的区域中的第一栅极氧化物层的第一子步骤以及在该区域上生长第二氧化物栅极层的第二子步骤，第二栅极氧化物层具有与第一栅极氧化物层不同的厚度。

103. 发明授权

US06319780B2 Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage 有权
标题翻译：用于制造用于低电压的MOS晶体管，用于高电压的用于低电压，EPROM单元和MOS晶体管的集成电路的工艺
公开(公告)号：US06319780B2
公开(公告)日：2001-11-20
申请号：US09727266
申请日：2000-11-29
申请人： Barbara Crivelli , Daniela Peschiaroli , Elisabetta Palumbo , Nicola Zatelli
发明人： Barbara Crivelli , Daniela Peschiaroli , Elisabetta Palumbo , Nicola Zatelli
IPC分类号： H01L218234
CPC分类号： H01L27/11526 , H01L27/1052 , H01L27/11539 , Y10S438/981
摘要： Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the thermal oxide layer. The polycrystalline silicon layer is selectively removed to form the floating gate electrodes of the EPROM cells, and the source and drain regions of the EPROM cells are also formed. The active areas for the high voltage MOS transistors are exposed, and a layer of high temperature oxide is formed and nitrided. The active area for the low voltage MOS transistors are exposed, and a layer of thermal oxide is formed on the exposed areas. A second polycrystalline silicon layer is deposited, which is then selectively removed to form the gate electrodes of the low voltage and high voltage MOS transistors, and the control gate electrodes of the EPROM cells.
摘要翻译：有源区域和体区形成在用于形成低压MOS晶体管，高压MOS晶体管和EPROM单元的衬底中。在基板上形成热氧化层，在热氧化层上形成第一多晶硅层。选择性地去除多晶硅层以形成EPROM单元的浮置栅电极，并且还形成EPROM单元的源极和漏极区。高电压MOS晶体管的有源区域被暴露，形成一层高温氧化物并氮化。低电压MOS晶体管的有源区域被暴露，并且在暴露的区域上形成一层热氧化物。沉积第二多晶硅层，然后选择性地去除以形成低压和高压MOS晶体管的栅电极以及EPROM单元的控制栅电极。

104. 发明授权

US6114203A Method of manufacturing a MOS integrated circuit having components with different dielectrics 失效
标题翻译：制造具有不同电介质的元件的MOS集成电路的方法
公开(公告)号：US6114203A
公开(公告)日：2000-09-05
申请号：US644892
申请日：1996-05-10
申请人： Gabriella Ghidini , Cesare Clementi
发明人： Gabriella Ghidini , Cesare Clementi
IPC分类号： H01L21/314 , H01L21/8239 , H01L21/8242 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/11526 , H01L21/3145 , H01L27/105 , H01L27/1052 , H01L27/10844 , H01L27/11539
摘要： The method described provides for the formation of thin thermal oxide on areas of a silicon die intended for memory cells and other components of the peripheral circuits of the memory. To improve the quality of the oxide of the cells essentially in terms of resistance to degradation due to the passage of charges through it during the operation of the memory, the method provides for a step for the high-temperature nitriding of the oxide. According to a variant, the nitrided oxide formed on the areas intended for the components of the peripheral circuits is removed and then formed again by a similar thermal oxidation treatment followed by high-temperature nitriding.
摘要翻译：所描述的方法提供了在用于存储器单元的硅芯片和存储器的外围电路的其他部件的区域上形成薄热氧化物。为了提高电池的氧化物的质量，基本上在记忆体的操作期间由于电荷通过它而导致的降解性的降低，该方法提供了氧化物的高温氮化的步骤。根据一个变型，在用于外围电路的部件的区域上形成的氮化氧化物被除去，然后通过类似的热氧化处理再次形成，然后进行高温氮化。

105. 发明授权

US6034416A Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US6034416A
公开(公告)日：2000-03-07
申请号：US61071
申请日：1998-04-16
申请人： Takashi Uehara , Toshiki Yabu , Mizuki Segawa , Takaaki Ukeda , Masatoshi Arai , Masaru Moriwaki
发明人： Takashi Uehara , Toshiki Yabu , Mizuki Segawa , Takaaki Ukeda , Masatoshi Arai , Masaru Moriwaki
IPC分类号： H01L21/8247 , H01L29/72
CPC分类号： H01L27/11526 , H01L27/11539
摘要： The top surface of a substrate in a peripheral circuit region is at a level that is higher than the top surface of the substrate in a memory cell region and that is substantially equal to the top surface of a floating gate electrode. A control gate electrode is formed on the floating gate electrode via a gate insulator film, and a gate electrode is formed on the substrate in the peripheral circuit region via a gate insulator film. The top surface of a buried insulator film for trench isolation may be at a level equal to the top surface of the floating gate electrode or to the top surface of an underlying film if the control gate electrode is formed of a multi-layer film. A level difference between the control gate electrode in the memory cell region and the gate electrode in the peripheral circuit region can be reduced, and thus fine patterns can be formed in these regions. In a flash-integrated logic LSI incorporating a nonvolatile memory cell, a density can be increased in the memory cell region and the peripheral circuit region and the costs can be reduced.
摘要翻译：外围电路区域中的衬底的顶表面处于比存储单元区域中的衬底顶表面高的位置，并且基本上等于浮栅电极的顶表面。通过栅极绝缘膜在浮栅上形成控制栅电极，通过栅极绝缘膜在外围电路区域的基板上形成栅电极。如果控制栅电极由多层膜形成，用于沟槽隔离的掩埋绝缘膜的顶表面可以处于等于浮栅电极的顶表面或底层膜的顶表面的水平。可以减小存储单元区域中的控制栅电极与外围电路区域中的栅电极之间的电平差，从而可以在这些区域中形成精细图案。在包含非易失性存储单元的闪存集成逻辑LSI中，可以在存储单元区域和外围电路区域中增加密度，并且可以降低成本。

106. 发明授权

US5063431A Semiconductor device having a two-layer gate structure 失效
标题翻译：具有两层门结构的半导体器件
公开(公告)号：US5063431A
公开(公告)日：1991-11-05
申请号：US226098
申请日：1988-07-29
申请人： Yohichi Ohshima
发明人： Yohichi Ohshima
IPC分类号： H01L27/112 , H01L21/28 , H01L21/8246 , H01L21/8247 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/11539 , H01L27/11543 , H01L29/511 , H01L29/7885 , H01L21/28211
摘要： A semiconductor device is disclosed, which comprises source and drain regions formed in a spaced-apart relation to each other on an isolated semiconductor substrate surface, a first conductive layer formed over a channel region between the source and drain regions via a gate insulating film and serving as a floating gate electrode, a two-layer insulating layer formed on the first conductive layer and consisting of a silicon oxynitride film and a silicon oxide film, and a second conductive layer formed on the two-layer insulating layer and serving as a control gate electrode. In the semiconductor device of this structure, the silicon oxynitride film traps fewer electrons, and electrons are infrequently trapped at the time of data erasing, so that data-erasing characteristics can be improved. Further, since fewer electrons are trapped, unlike the prior art insulating layer utilizing a silicon nitride film, there is no need for providing any silicon oxide film on each side, and with the two-layer structure consisting of the silicon oxynitride film and a silicon oxide film it is possible to obtain sufficient insulation and film thickness reduction.

107. 发明授权

US4822750A MOS floating gate memory cell containing tunneling diffusion region in contact with drain and extending under edges of field oxide 失效
标题翻译： MOS浮动存储单元包含与漏极接触并在场氧化物的边缘下延伸的隧道扩散区域
公开(公告)号：US4822750A
公开(公告)日：1989-04-18
申请号：US74085
申请日：1987-07-16
申请人： Gust Perlegos , Tsung-Ching Wu
发明人： Gust Perlegos , Tsung-Ching Wu
IPC分类号： H01L21/8247 , H01L27/115 , H01L27/04 , H01L27/13
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11529 , H01L27/11539 , H01L27/11546
摘要： A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel of the memory device in the substrate and wherein an implanted region in the substrate to facilitate the tunneling of carriers in and out of the floating gate extends appreciably underneath the edges of the field oxide regions forming the periphery of the sides of the channel of the memory device. A select device is located in series with the memory device. A process for fabricating this memory cell is also disclosed wherein the doped tunnelling region in the substrate is defined and implanted prior to definition of the field regions.
摘要翻译：公开了一种双器件浮置栅MOS非易失性存储单元，其包括耦合到选择器件的浮动栅极存储器件，其中存储器件的衬底和浮置栅极之间的绝缘材料的薄隧道电介质区域位于衬底中的存储器件，并且其中衬底中的用于促进载流子进入和离开浮置栅极的隧穿的衬底中的注入区域明显地在形成存储器件的沟道的边的周边的场氧化物区域的边缘下方延伸。选择设备与存储设备串联。还公开了一种用于制造该存储器单元的工艺，其中在定义场区之前限定和注入衬底中的掺杂隧道区。

108. 发明授权

US10014308B2 Electronic chip manufacturing method 有权
公开(公告)号：US10014308B2
公开(公告)日：2018-07-03
申请号：US15228236
申请日：2016-08-04
申请人： STMicroelectronics (Crolles 2) SAS
发明人： Stephane Zoll , Philippe Garnier
IPC分类号： H01L27/105 , H01L27/11539 , H01L29/788 , H01L21/28 , H01L27/11521
CPC分类号： H01L27/11539 , H01L27/11521 , H01L27/11536 , H01L29/40114 , H01L29/40117 , H01L29/42368 , H01L29/495 , H01L29/513 , H01L29/518 , H01L29/7887
摘要： Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

109. 发明授权

US09842845B1 Method of forming a semiconductor device structure and semiconductor device structure 有权
公开(公告)号：US09842845B1
公开(公告)日：2017-12-12
申请号：US15337441
申请日：2016-10-28
申请人： GLOBALFOUNDRIES Inc.
发明人： Thomas Melde , Ralf Richter
IPC分类号： H01L29/788 , H01L29/792 , H01L21/8238 , H01L21/336 , H01L27/11531 , H01L27/11521 , H01L29/423 , H01L29/66 , H01L21/28 , H01L21/311 , H01L29/49
CPC分类号： H01L27/11531 , H01L21/28035 , H01L21/28273 , H01L21/31111 , H01L27/11521 , H01L27/11524 , H01L27/11536 , H01L27/11539 , H01L29/42328 , H01L29/4916 , H01L29/66825 , H01L29/788 , H01L29/7881
摘要： The present disclosure provides a semiconductor device structure including a non-volatile memory (NVM) device structure in and above a first region of a semiconductor substrate and a logic device formed in and above a second region of the semiconductor substrate different from the first region. The NVM device structure includes a floating-gate, a first select gate and at least one control gate. The logic device includes a logic gate disposed on the second region and source/drain regions provided in the second region adjacent to the logic gate. The control gate extends over the floating-gate and the first select gate is laterally separated from the floating-gate by an insulating material layer portion. Upon forming the semiconductor device structure, the floating gate is formed before forming the control gate and the logic device.

110. 发明授权

US09659948B2 Semiconductor device and method of fabricating semiconductor device 有权
公开(公告)号：US09659948B2
公开(公告)日：2017-05-23
申请号：US14856577
申请日：2015-09-17
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chia-Ching Hsu , Ko-Chi Chen , Shen-De Wang
IPC分类号： H01L27/11529 , H01L27/11573 , H01L27/11531
CPC分类号： H01L27/11529 , H01L27/11524 , H01L27/11531 , H01L27/11536 , H01L27/11539 , H01L27/11573
摘要： A semiconductor device includes a substrate with a memory region and a logic region, a logic gate stack, and a non-volatile gate stack. The substrate has a recess disposed in the memory region. The logic gate stack is disposed in the logic region and has a first top surface. The non-volatile gate stack is disposed in the recess and has a second top surface. The second top surface is lower than the first top surface by a step height.

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