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1. 发明授权

US06319780B2 Process for the fabrication of an integrated circuit comprising MOS transistors for low voltage, EPROM cells and MOS transistors for high voltage 有权
标题翻译：用于制造用于低电压的MOS晶体管，用于高电压的用于低电压，EPROM单元和MOS晶体管的集成电路的工艺
公开(公告)号：US06319780B2
公开(公告)日：2001-11-20
申请号：US09727266
申请日：2000-11-29
申请人： Barbara Crivelli , Daniela Peschiaroli , Elisabetta Palumbo , Nicola Zatelli
发明人： Barbara Crivelli , Daniela Peschiaroli , Elisabetta Palumbo , Nicola Zatelli
IPC分类号： H01L218234
CPC分类号： H01L27/11526 , H01L27/1052 , H01L27/11539 , Y10S438/981
摘要： Active areas and body regions are formed in a substrate for forming low voltage MOS transistors, high voltage MOS transistors, and EPROM cells. A thermal oxide layer is formed on the substrate, and a first polycrystalline silicon layer is formed on the thermal oxide layer. The polycrystalline silicon layer is selectively removed to form the floating gate electrodes of the EPROM cells, and the source and drain regions of the EPROM cells are also formed. The active areas for the high voltage MOS transistors are exposed, and a layer of high temperature oxide is formed and nitrided. The active area for the low voltage MOS transistors are exposed, and a layer of thermal oxide is formed on the exposed areas. A second polycrystalline silicon layer is deposited, which is then selectively removed to form the gate electrodes of the low voltage and high voltage MOS transistors, and the control gate electrodes of the EPROM cells.
摘要翻译：有源区域和体区形成在用于形成低压MOS晶体管，高压MOS晶体管和EPROM单元的衬底中。在基板上形成热氧化层，在热氧化层上形成第一多晶硅层。选择性地去除多晶硅层以形成EPROM单元的浮置栅电极，并且还形成EPROM单元的源极和漏极区。高电压MOS晶体管的有源区域被暴露，形成一层高温氧化物并氮化。低电压MOS晶体管的有源区域被暴露，并且在暴露的区域上形成一层热氧化物。沉积第二多晶硅层，然后选择性地去除以形成低压和高压MOS晶体管的栅电极以及EPROM单元的控制栅电极。

2. 发明授权

US06627928B2 Method of manufacturing an integrated circuit, for integrating an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip 有权
标题翻译：用于将电可编程，非易失性存储器和高性能逻辑电路集成在同一半导体芯片中的集成电路的制造方法
公开(公告)号：US06627928B2
公开(公告)日：2003-09-30
申请号：US10261987
申请日：2002-10-01
申请人： Daniela Peschiaroli , Alfonso Maurelli , Elisabetta Palumbo , Fausto Piazza
发明人： Daniela Peschiaroli , Alfonso Maurelli , Elisabetta Palumbo , Fausto Piazza
IPC分类号： H01L2976
CPC分类号： H01L27/11526 , H01L27/1052 , H01L27/11541
摘要： A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.
摘要翻译：一种用于制造具有存储器件和逻辑电路的集成电路的方法，包括在半导体衬底的第一部分中形成多个第一晶体管，在半导体衬底的第二部分中形成多个第二晶体管，以及多个存储器在半导体衬底的第三部分中的单元。用于从半导体衬底的第一和第三部分选择性地去除电介质层的矩阵掩模允许电介质保留在多个存储单元的浮置栅极和多个第一晶体管的栅电极上。然后在浮动栅极上形成控制栅极，该栅极由电介质分离。多个第一晶体管的栅电极的一部分保持自由，以便与晶体管接触。

3. 发明授权

US06482698B2 Method of manufacturing an electrically programmable, non-volatile memory and high-performance logic circuitry in the same semiconductor chip 有权
标题翻译：在同一半导体芯片中制造电可编程，非易失性存储器和高性能逻辑电路的方法
公开(公告)号：US06482698B2
公开(公告)日：2002-11-19
申请号：US09817799
申请日：2001-03-26
申请人： Daniela Peschiaroli , Alfonso Maurelli , Elisabetta Palumbo , Fausto Piazza
发明人： Daniela Peschiaroli , Alfonso Maurelli , Elisabetta Palumbo , Fausto Piazza
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/1052 , H01L27/11541
摘要： A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.
摘要翻译：一种用于制造具有存储器件和逻辑电路的集成电路的方法，包括在半导体衬底的第一部分中形成多个第一晶体管，在半导体衬底的第二部分中形成多个第二晶体管，以及多个存储器在半导体衬底的第三部分中的单元。用于从半导体衬底的第一和第三部分选择性地去除电介质层的矩阵掩模允许电介质保留在多个存储单元的浮置栅极和多个第一晶体管的栅电极上。然后在浮动栅极上形成控制栅极，该栅极由电介质分离。多个第一晶体管的栅电极的一部分保持自由，以便与晶体管接触。

4. 发明申请

US20070026610A1 SEALING METHOD FOR ELECTRONIC DEVICES FORMED ON A COMMON SEMICONDUCTOR SUBSTRATE AND CORRESPONDING CIRCUIT STRUCTURE 审中-公开
标题翻译：在通用半导体基板上形成的电子器件的密封方法和相应的电路结构
公开(公告)号：US20070026610A1
公开(公告)日：2007-02-01
申请号：US11457948
申请日：2006-07-17
申请人： Emilio Camerlenghi , Alfonso Maurelli , Daniela Peschiaroli , Paola Zabberoni
发明人： Emilio Camerlenghi , Alfonso Maurelli , Daniela Peschiaroli , Paola Zabberoni
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823468 , H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： An integrated circuit includes a semiconductor substrate including first and second portions, with first electronic devices adjacent the first portion. Each first electronic device includes a first region comprising at least one first conductive layer projecting from the semiconductor substrate. First protective spacers are adjacent sidewalls of the first regions of the first electronic devices. The first protective spacers are defined by first and second sealing layers adjacent one another. Second electronic devices are adjacent the second portion of the semiconductor substrate. Each second electronic device includes a second region comprising a second conductive layer projecting from the semiconductor substrate. Second protective spacers are adjacent sidewalls of the second regions of the second electronic devices. The second protective spacers are defined by other portions of the second sealing layer. The second sealing layer has a thickness less than a thickness of the first sealing layer.
摘要翻译：集成电路包括包括第一和第二部分的半导体衬底，第一电子器件与第一部分相邻。每个第一电子器件包括包含从半导体衬底突出的至少一个第一导电层的第一区域。第一保护间隔物是第一电子器件的第一区域的相邻侧壁。第一保护隔离物由彼此相邻的第一和第二密封层限定。第二电子器件与半导体衬底的第二部分相邻。每个第二电子器件包括第二区域，其包括从半导体衬底突出的第二导电层。第二保护间隔物是第二电子器件的第二区域的相邻侧壁。第二保护隔离物由第二密封层的其它部分限定。第二密封层的厚度小于第一密封层的厚度。

5. 发明申请

US20070287290A1 MANUFACTURING METHOD FOR NON-ACTIVE ELECTRICALLY STRUCTURES OF AN INTEGRATED ELECTRONIC CIRCUIT FORMED ON A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING ELECTRONIC CIRCUIT 审中-公开
标题翻译：在半导体基板和相应电子电路上形成的集成电子电路的非主动电气结构的制造方法
公开(公告)号：US20070287290A1
公开(公告)日：2007-12-13
申请号：US11754494
申请日：2007-05-29
申请人： Alfonso Maurelli , Daniela Peschiaroli , Fausto Piazza , Carlo Vigiani , Paola Zabberoni
发明人： Alfonso Maurelli , Daniela Peschiaroli , Fausto Piazza , Carlo Vigiani , Paola Zabberoni
IPC分类号： H01L21/302 , H01L21/31
CPC分类号： H01L27/11526 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/11519 , H01L27/11534
摘要： Electrically non-active structures are formed for an electronic circuit to make uniform a surface above a semiconductor substrate. The electronic circuit includes first electrically active structures comprising conductive elements of a first height projecting from the semiconductor substrate, and second electrically active structures comprising conductive elements of a second height projecting from the semiconductor substrate. The first height is different from the second height. The electrically non-active structures are formed by identifying, among the electrically non-active structures, a first group of electrically non-active structures formed within areas that substantially extend for a radius around each electrical component belonging to the second electrically active structures. The method further includes identifying, among the electrically non-active structures, a second group of electrically non-active structures not belonging to the first group of electrically non-active structures. The electrically non-active structures belonging to the first group of electrically non-active structures are formed with elements projecting from the semiconductor substrate having a height equal to the second height. The electrically non-active structures belonging to the second group of electrically non-active structures are formed with elements projecting from the semiconductor substrate having a height equal to the first height.
摘要翻译：形成用于电子电路的电非结构以在半导体衬底上方形成均匀的表面。电子电路包括第一电活动结构，其包括从半导体衬底突出的第一高度的导电元件，以及包括从半导体衬底突出的第二高度的导电元件的第二电活动结构。第一高度与第二高度不同。电非活性结构通过在电非活性结构之中识别形成在基本上延伸用于围绕属于第二电活动结构的每个电气部件的半径的区域内的第一组电非活性结构而形成。该方法还包括在电非活性结构中识别不属于第一组电非活性结构的第二组电非活性结构。属于第一组电非活性结构的电非活性结构由具有等于第二高度的高度从半导体衬底突出的元件形成。属于第二组电非活性结构的电非活性结构由具有等于第一高度的高度的半导体衬底突出的元件形成。

6. 发明授权

US07078294B2 Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure 有权
标题翻译：形成在公共半导体衬底上的电子器件的密封方法和相应的电路结构
公开(公告)号：US07078294B2
公开(公告)日：2006-07-18
申请号：US10971774
申请日：2004-10-22
申请人： Emilio Camerlenghi , Alfonso Maurelli , Daniela Peschiaroli , Paola Zabberoni
发明人： Emilio Camerlenghi , Alfonso Maurelli , Daniela Peschiaroli , Paola Zabberoni
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L23/3192 , H01L27/105 , H01L27/11536 , H01L2924/0002 , H01L2924/00
摘要： A method for sealing electronic devices formed on a semiconductor substrate includes forming at least one first conductive layer on a first portion of the semiconductor substrate for defining electronic devices, and forming a second conductive layer on a second portion of semiconductor substrate for also defining electronic devices. First regions are formed in the at least one first conductive layer for defining electronic devices, and a first sealing layer is formed on the whole semiconductor substrate to seal the first regions. Second regions are formed in the second conductive layer for defining electronic devices, and a second sealing layer is formed on the whole semiconductor substrate to seal the second regions.
摘要翻译：用于密封形成在半导体衬底上的电子器件的方法包括在半导体衬底的用于限定电子器件的第一部分上形成至少一个第一导电层，以及在半导体衬底的第二部分上形成第二导电层，用于还限定电子器件。第一区域形成在用于限定电子器件的至少一个第一导电层中，并且在整个半导体衬底上形成第一密封层以密封第一区域。第二区域形成在用于限定电子器件的第二导电层中，并且在整个半导体衬底上形成第二密封层以密封第二区域。

7. 发明申请

US20050112905A1 Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure 有权
标题翻译：形成在公共半导体衬底上的电子器件的密封方法和相应的电路结构
公开(公告)号：US20050112905A1
公开(公告)日：2005-05-26
申请号：US10971774
申请日：2004-10-22
申请人： Emilio Camerlenghi , Alfonso Maurelli , Daniela Peschiaroli , Paola Zabberoni
发明人： Emilio Camerlenghi , Alfonso Maurelli , Daniela Peschiaroli , Paola Zabberoni
IPC分类号： H01L21/8234 , H01L21/8247 , H01L23/31 , H01L27/105 , H01L21/44 , B32B7/12 , B32B15/04 , H01L21/31 , H01L21/469 , H01L21/48 , H01L21/50
CPC分类号： H01L27/11526 , H01L21/823468 , H01L23/3192 , H01L27/105 , H01L27/11536 , H01L2924/0002 , H01L2924/00
摘要： A method for sealing electronic devices formed on a semiconductor substrate includes forming at least one first conductive layer on a first portion of the semiconductor substrate for defining electronic devices, and forming a second conductive layer on a second portion of semiconductor substrate for also defining electronic devices. First regions are formed in the at least one first conductive layer for defining electronic devices, and a first sealing layer is formed on the whole semiconductor substrate to seal the first regions. Second regions are formed in the second conductive layer for defining electronic devices, and a second sealing layer is formed on the whole semiconductor substrate to seal the second regions.
摘要翻译：用于密封形成在半导体衬底上的电子器件的方法包括在半导体衬底的用于限定电子器件的第一部分上形成至少一个第一导电层，以及在半导体衬底的第二部分上形成第二导电层，用于还限定电子器件。第一区域形成在用于限定电子器件的至少一个第一导电层中，并且在整个半导体衬底上形成第一密封层以密封第一区域。第二区域形成在用于限定电子器件的第二导电层中，并且在整个半导体衬底上形成第二密封层以密封第二区域。

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