专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6069055A Fabricating method for semiconductor device 失效
标题翻译：半导体器件制造方法
公开(公告)号：US6069055A
公开(公告)日：2000-05-30
申请号：US886859
申请日：1997-07-01
申请人： Takaaki Ukeda , Toshiki Yabu , Takashi Uehara , Mizuki Segawa , Masatoshi Arai , Masaru Moriwaki
发明人： Takaaki Ukeda , Toshiki Yabu , Takashi Uehara , Mizuki Segawa , Masatoshi Arai , Masaru Moriwaki
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/76232
摘要： The fabricating method for semiconductor devices in which the trench technique is employed to perform isolation between devices, and which comprises the steps of sequentially depositing a first film 2, 3 and a second film 4 on top of a silicon substrate 1, forming an element isolation trench 5 in the silicon substrate 1 with masking of the first film 2, 3 and second film 4 which have undergone patterning, and growing a silicon oxide film 6 that is generated by reaction of ozone and tetra-ethyl-ortho-silicate inside the element isolation trench where silicon is exposed.
摘要翻译：采用沟槽技术来进行器件之间的隔离的半导体器件的制造方法，其包括以下步骤：在硅衬底1的顶部依次沉积第一膜2,3和第二膜4，形成元件隔离硅衬底1中的沟槽5，其具有被图案化的第一膜2,3和第二膜4的掩蔽，并且通过在元件内的臭氧和四乙基原硅酸盐的反应产生氧化硅膜6 硅暴露的隔离沟槽。

2. 发明授权

US6034416A Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US6034416A
公开(公告)日：2000-03-07
申请号：US61071
申请日：1998-04-16
申请人： Takashi Uehara , Toshiki Yabu , Mizuki Segawa , Takaaki Ukeda , Masatoshi Arai , Masaru Moriwaki
发明人： Takashi Uehara , Toshiki Yabu , Mizuki Segawa , Takaaki Ukeda , Masatoshi Arai , Masaru Moriwaki
IPC分类号： H01L21/8247 , H01L29/72
CPC分类号： H01L27/11526 , H01L27/11539
摘要： The top surface of a substrate in a peripheral circuit region is at a level that is higher than the top surface of the substrate in a memory cell region and that is substantially equal to the top surface of a floating gate electrode. A control gate electrode is formed on the floating gate electrode via a gate insulator film, and a gate electrode is formed on the substrate in the peripheral circuit region via a gate insulator film. The top surface of a buried insulator film for trench isolation may be at a level equal to the top surface of the floating gate electrode or to the top surface of an underlying film if the control gate electrode is formed of a multi-layer film. A level difference between the control gate electrode in the memory cell region and the gate electrode in the peripheral circuit region can be reduced, and thus fine patterns can be formed in these regions. In a flash-integrated logic LSI incorporating a nonvolatile memory cell, a density can be increased in the memory cell region and the peripheral circuit region and the costs can be reduced.
摘要翻译：外围电路区域中的衬底的顶表面处于比存储单元区域中的衬底顶表面高的位置，并且基本上等于浮栅电极的顶表面。通过栅极绝缘膜在浮栅上形成控制栅电极，通过栅极绝缘膜在外围电路区域的基板上形成栅电极。如果控制栅电极由多层膜形成，用于沟槽隔离的掩埋绝缘膜的顶表面可以处于等于浮栅电极的顶表面或底层膜的顶表面的水平。可以减小存储单元区域中的控制栅电极与外围电路区域中的栅电极之间的电平差，从而可以在这些区域中形成精细图案。在包含非易失性存储单元的闪存集成逻辑LSI中，可以在存储单元区域和外围电路区域中增加密度，并且可以降低成本。

3. 发明授权

US07126174B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07126174B2
公开(公告)日：2006-10-24
申请号：US10995283
申请日：2004-11-24
申请人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
发明人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
IPC分类号： H01L29/76
CPC分类号： H01L29/6659 , H01L21/76224 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.
摘要翻译：形成了比硅衬底的有源区域更高级的隔离。在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中杂质浓度低的部分接触。以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。

4. 发明申请

US20050093089A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050093089A1
公开(公告)日：2005-05-05
申请号：US10995283
申请日：2004-11-24
申请人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
发明人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8242 , H01L29/00
CPC分类号： H01L29/6659 , H01L21/76224 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.
摘要翻译：形成了比硅衬底的有源区域更高级的隔离。在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中杂质浓度低的部分接触。以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。

5. 发明授权

US6124160A Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US6124160A
公开(公告)日：2000-09-26
申请号：US192536
申请日：1998-11-17
申请人： Mizuki Segawa , Toshiki Yabu , Takashi Uehara , Takashi Nakabayashi , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada
发明人： Mizuki Segawa , Toshiki Yabu , Takashi Uehara , Takashi Nakabayashi , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada
IPC分类号： H01L29/43 , H01L21/02 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/06 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/8242
CPC分类号： H01L27/11526 , H01L21/82345 , H01L27/0629 , H01L27/105 , H01L27/11543 , H01L28/40 , Y10S438/957
摘要： A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled. In the semiconductor device in which a transistor, a capacitive element, a resistive film and the like are provided, the occupied area can be reduced and the manufacturing cost can be cut down.
摘要翻译： MOS晶体管包括栅极氧化膜和通过第一和第二导体膜的叠层形成的栅电极。电容元件包括由第一导体膜形成的下部电容电极，由与栅极氧化膜不同的绝缘膜制成的电容膜，由电容膜上的第二导体膜形成的上部电容电极，以及引线电极由第二导电膜形成。以与使用栅极氧化膜作为电容膜的情况相同的步骤，可以制造具有设置的电容膜的半导体器件，电容膜由与氮化物膜不同的氮化物膜等构成栅氧化膜。因此，使用具有每单位面积的大的电容值的电容膜，从而可以减小占用面积并且可以控制制造成本的增加。在其中提供晶体管，电容元件，电阻膜等的半导体器件中，可以减小占用面积并且可以减少制造成本。

6. 发明申请

US20050156220A1 Semiconductor device and method of manufacturing the same 审中-公开
公开(公告)号：US20050156220A1
公开(公告)日：2005-07-21
申请号：US11081679
申请日：2005-03-17
申请人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
发明人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
IPC分类号： H01L21/336 , H01L21/762 , H01L27/108 , H01L21/8242
CPC分类号： H01L29/6659 , H01L21/76224 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

7. 发明授权

US06847119B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US06847119B2
公开(公告)日：2005-01-25
申请号：US10454682
申请日：2003-06-05
申请人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
发明人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

8. 发明授权

US06709950B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06709950B2
公开(公告)日：2004-03-23
申请号：US09902157
申请日：2001-07-11
申请人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
发明人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
IPC分类号： H01L29167
CPC分类号： H01L29/6659 , H01L21/76224 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.
摘要翻译：形成了比硅衬底的有源区域更高级的隔离。在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中杂质浓度低的部分接触。以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。

9. 发明授权

US06492672B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06492672B1
公开(公告)日：2002-12-10
申请号：US09629861
申请日：2000-08-01
申请人： Mizuki Segawa , Toshiki Yabu , Takashi Uehara , Takashi Nakabayashi , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada
发明人： Mizuki Segawa , Toshiki Yabu , Takashi Uehara , Takashi Nakabayashi , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada
IPC分类号： H01L27108
CPC分类号： H01L27/11526 , H01L21/82345 , H01L27/0629 , H01L27/105 , H01L27/11543 , H01L28/40 , Y10S438/957
摘要： A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled. In the semiconductor device in which a transistor, a capacitive element, a resistive film and the like are provided, the occupied area can be reduced and the manufacturing cost can be cut down.
摘要翻译： MOS晶体管包括栅极氧化膜和通过第一和第二导体膜的叠层形成的栅电极。电容元件包括由第一导体膜形成的下部电容电极，由与栅极氧化膜不同的绝缘膜制成的电容膜，由电容膜上的第二导体膜形成的上部电容电极，以及引线电极由第二导电膜形成。以与使用栅极氧化膜作为电容膜的情况相同的步骤，可以制造具有设置的电容膜的半导体器件，电容膜由与氮化物膜不同的氮化物膜等构成栅氧化膜。因此，使用具有每单位面积的大的电容值的电容膜，从而可以减小占用面积并且可以控制制造成本的增加。在其中提供晶体管，电容元件，电阻膜等的半导体器件中，可以减小占用面积并且可以减少制造成本。

10. 发明授权

US06281562B1 Semiconductor device which reduces the minimum distance requirements between active areas 失效
标题翻译：降低有效区域之间最小距离要求的半导体器件
公开(公告)号：US06281562B1
公开(公告)日：2001-08-28
申请号：US08685726
申请日：1996-07-24
申请人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
发明人： Mizuki Segawa , Isao Miyanaga , Toshiki Yabu , Takashi Nakabayashi , Takashi Uehara , Kyoji Yamashita , Takaaki Ukeda , Masatoshi Arai , Takayuki Yamada , Michikazu Matsumoto
IPC分类号： H01L29167
CPC分类号： H01L29/6659 , H01L21/76224 , H01L29/665 , H01L2924/0002 , H01L2924/00
摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.
摘要翻译：形成了比硅衬底的有源区域更高级的隔离。在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中的杂质浓度低的部分接触。以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式