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101. 发明申请

US20110019492A1 TEST DEVICE AND TEST METHOD FOR RESISTIVE RANDOM ACCESS MEMORY AND RESISTIVE RANDOM ACCESS MEMORY DEVICE 审中-公开
标题翻译：电阻随机访问存储器和电阻随机访问存储器件的测试装置和测试方法
公开(公告)号：US20110019492A1
公开(公告)日：2011-01-27
申请号：US12752646
申请日：2010-04-01
申请人： Kazuaki KAWAGUCHI , Kazushige KANDA
发明人： Kazuaki KAWAGUCHI , Kazushige KANDA
IPC分类号： G11C29/00 , G11C11/00
CPC分类号： G11C29/56 , G11C19/28 , G11C29/56012
摘要： A first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted.
摘要翻译：输入第一写入使能信号，其以检查字线的激活/去激活控制和位线的激活/去激活控制之间的限制时间的时间部分上变化的恒定周期和第二写使能信号进行改变，产生多个核心控制信号，其中核心控制信号改变的时间间隔基于输入的第一写入使能信号和第二写入使能信号而局部地短于第一写入使能信号的周期，并且通过使用所生成的核心控制信号来执行电阻式随机存取存储器的操作验证，由此本地和任意调整任意测试周期中的周期时间。

102. 发明申请

US20100262397A1 MULTIPLY APPARATUS FOR SEMICONDUCTOR TEST PATTERN SIGNAL 有权
标题翻译：用于半导体测试模式信号的多用途设备
公开(公告)号：US20100262397A1
公开(公告)日：2010-10-14
申请号：US12739557
申请日：2008-10-17
申请人： Kyung-hun Chang , Se-kyung Oh
发明人： Kyung-hun Chang , Se-kyung Oh
IPC分类号： G06F19/00 , G01R31/26
CPC分类号： G11C29/56 , G01R31/31928 , G11C29/56004 , G11C29/56012
摘要： An apparatus for multiplying a semiconductor test pattern signal is disclosed. The multiplying apparatus firstly encodes a plurality of pattern signals to have different pattern types, and multiplies the encoded pattern signals according to an exclusive-OR (XOR) scheme in order to generate a single pattern signal, thereby recognizing a relationship between a pattern signal before the multiplication and the other pattern signal after the multiplication. A pattern-signal segmenting/outputting unit segments a semiconductor test pattern signal into a plurality of pattern signals, and simultaneously outputs the segmented pattern signals. A pattern-signal restoring/multiplying unit restores the segmented pattern signals received from the pattern-signal segmenting/outputting unit to the semiconductor test pattern signal, outputs the restored result to a driver which records a test pattern in an objective semiconductor to be tested, and multiplies the signal outputted to the driver by a predetermined frequency band rather than a frequency band of the segmented signals.
摘要翻译：公开了一种用于乘以半导体测试图案信号的装置。乘法装置首先对多个图案信号进行编码以具有不同的图案类型，并且根据异或（XOR）方式对编码图案信号进行乘法，以便生成单个图案信号，从而识别出之前的图案信号之间的关系乘法和乘法后的其他模式信号。图案信号分割/输出单元将半导体测试图案信号分割成多个图案信号，并且同时输出分割的图案信号。模式信号恢复/乘法单元将从图案信号分割/输出单元接收到的分段图形信号恢复到半导体测试图形信号，将恢复结果输出到测试图案记录在要测试的目标半导体中的驱动器，并且将输出到驱动器的信号乘以预定频带而不是分段信号的频带。

103. 发明授权

US07777513B2 Power supply voltage detection circuit and semiconductor integrated circuit device 失效
标题翻译：电源电压检测电路和半导体集成电路器件
公开(公告)号：US07777513B2
公开(公告)日：2010-08-17
申请号：US12213512
申请日：2008-06-20
申请人： Manabu Kitabatake , Yuji Tada , Kouji Naganawa , Tsuyoshi Hirakawa , Ichiro Mizuguchi
发明人： Manabu Kitabatake , Yuji Tada , Kouji Naganawa , Tsuyoshi Hirakawa , Ichiro Mizuguchi
IPC分类号： G01R31/26
CPC分类号： G01R31/31726 , G11C29/1201 , G11C29/12015 , G11C29/14 , G11C29/48 , G11C29/50012 , G11C29/56012 , G11C2029/0401 , G11C2029/5602 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device includes a first chip, a second chip to transmit and receive data to and from the first chip, and a through circuit provided in the first chip to transfer a clock signal and a test signal to the second chip. The clock signal and the test signal is inputted from an external device. The through circuit adjusts timing relation between the clock signal and the test signal based on a timing adjust signal. The timing adjust signal is inputted from the external device.
摘要翻译：半导体集成电路器件包括第一芯片，向第一芯片发送数据和从第一芯片接收数据的第二芯片，以及设置在第一芯片中的通过电路，将时钟信号和测试信号传送到第二芯片。时钟信号和测试信号从外部设备输入。通过电路基于定时调整信号调整时钟信号和测试信号之间的时序关系。定时调整信号从外部设备输入。

104. 发明申请

US20100195426A1 Semiconductor memory device and method of testing the same 失效
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US20100195426A1
公开(公告)日：2010-08-05
申请号：US12656521
申请日：2010-02-02
申请人： Akiyoshi Yamamoto
发明人： Akiyoshi Yamamoto
IPC分类号： G11C29/00 , G11C8/18
CPC分类号： G11C8/18 , G11C29/50 , G11C29/50012 , G11C29/56 , G11C29/56012
摘要： A device and a method controlling the device are provided. A first command is supplied to the device in synchronization with a clock signal of a first frequency. The first command is to have the device perform a first operation. The frequency of the clock signal is changed from the first frequency to a second frequency higher than the first frequency. The device performs the first operation in synchronization with the clock signal of the second frequency following changing the frequency of the clock signal.
摘要翻译：提供了一种控制该设备的设备和方法。与第一频率的时钟信号同步地向设备提供第一命令。第一个命令是使设备执行第一个操作。时钟信号的频率从第一频率变为高于第一频率的第二频率。在改变时钟信号的频率之后，该装置与第二频率的时钟信号同步地执行第一操作。

105. 发明授权

US07710792B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07710792B2
公开(公告)日：2010-05-04
申请号：US12155171
申请日：2008-05-30
申请人： Minari Arai
发明人： Minari Arai
IPC分类号： G11C7/10
CPC分类号： G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/56012
摘要： Disclosed is a semiconductor device comprising: a signal selecting circuit for receiving, at first and second inputs thereof, respectively, a first signal output from a first initial-stage circuit that receives a data strobe signal from a first terminal, which is an input/output terminal, and a second signal output from a second initial-stage circuit that receives a data mask signal from a second terminal, which is an input terminal, and based upon a control signal that is supplied thereto, outputting the first and second signals from first and second outputs or interchanging the first and second signals and outputting the interchanged first and second signals from the second and first outputs; a buffer circuit for receiving an output signal from a third initial-stage circuit that receives a data signal from a data terminal; and a data latch circuit for latching a signal from the buffer circuit. The signal from the first output of the signal selecting circuit is supplied to the data latch circuit as a latch timing signal.
摘要翻译：公开了一种半导体器件，包括：信号选择电路，分别在其第一和第二输入处接收从第一初级电路输出的第一信号，该第一初级电路从作为输入/输出端的第一端接收数据选通信号，输出端子和从第二初始级电路输出的第二信号，该第二初始级电路从作为输入端的第二端子接收数据屏蔽信号，并且基于提供给其的控制信号，输出第一和第二信号第一和第二输出或交换第一和第二信号并输出来自第二和第一输出的互换的第一和第二信号; 缓冲电路，用于接收来自数据终端接收数据信号的第三初级电路的输出信号; 以及用于锁存来自缓冲电路的信号的数据锁存电路。来自信号选择电路的第一输出的信号作为锁存定时信号提供给数据锁存电路。

106. 发明申请

US20090282280A1 Memory System for seamless switching 有权
标题翻译：内存系统，无缝切换
公开(公告)号：US20090282280A1
公开(公告)日：2009-11-12
申请号：US12379276
申请日：2009-02-18
申请人： Hoe-ju Chung
发明人： Hoe-ju Chung
IPC分类号： G06F1/08
CPC分类号： G11C29/56012
摘要： Provided is a memory system for seamless switching. The memory system includes first through mth chips, where m is a natural number, connected in the form of a daisy chain and configured to transmit at least one of signals and data, a (k−1)th chip of the first through mth chips, where k is a natural number and 2≦k≦m, configured to output a (k−1)th detection signal corresponding to a phase difference between (k−1)th test data of the (k−1)th chip and kth test data of a kth chip of the first through mth chips, and the kth chip including a clock phase control unit configured to control a phase of a received clock signal and to output the phase-controlled clock signal as a kth clock signal, where the clock phase control unit of the kth chip outputs the kth clock signal in response to the (k−1)th detection signal.
摘要翻译：提供了一种用于无缝切换的存储器系统。存储器系统包括第一至第m个芯片，其中m是自然数，以菊链的形式连接并被配置为传输信号和数据中的至少一个，第一至第m个芯片的第（k-1）个芯片，其中k是自然数，2 <= k <= m，被配置为输出与第（k-1）次的第（k-1）个测试数据之间的相位差相对应的第（k-1）芯片和第k个测试数据，第k个芯片包括时钟相位控制单元，其被配置为控制接收的时钟信号的相位，并输出相位控制的时钟信号作为第k个时钟信号，其中第k个芯片的时钟相位控制单元响应于第（k-1）个检测信号输出第k个时钟信号。

107. 发明授权

US07567073B2 Interface circuit and memory controller 有权
标题翻译：接口电路和存储控制器
公开(公告)号：US07567073B2
公开(公告)日：2009-07-28
申请号：US11802846
申请日：2007-05-25
申请人： Takahiro Hori
发明人： Takahiro Hori
IPC分类号： G01R23/175 , G11C7/22 , G01P21/00
CPC分类号： G11C29/56 , G11C29/56012 , H04L1/243
摘要： A memory controller includes a variable delay circuit for phase-shifting a signal and an interface circuit suited for performing a test of a controller so that the memory controller realizes a test of a delay failure detection in a real-time speed operation at the time of the test.
摘要翻译：存储器控制器包括用于相移信号的可变延迟电路和适于执行控制器测试的接口电路，使得存储器控制器在实时速度操作中实现延迟故障检测的测试考试。

108. 发明授权

US07555686B2 Semiconductor device, test board for testing the same, and test system and method for testing the same 有权
标题翻译：半导体器件，用于测试的测试板，以及测试系统和测试方法
公开(公告)号：US07555686B2
公开(公告)日：2009-06-30
申请号：US11483753
申请日：2006-07-10
申请人： Woo-seop Kim
发明人： Woo-seop Kim
IPC分类号： G01R31/28
CPC分类号： G11C29/56 , G11C29/56012 , G11C2029/5602
摘要： Provided are a semiconductor device, a test board, and a test system and method for testing a semiconductor device. The semiconductor device includes an input terminal to which test pattern data is serially input at a first speed and an output terminal which one-to-one corresponds to the input terminal and serially outputs the test pattern data to the outside at a second speed that is different from the first speed.
摘要翻译：提供半导体器件，测试板以及用于测试半导体器件的测试系统和方法。半导体器件包括以第一速度串行输入测试图案数据的输入端子和一对一对应于输入端子的输出端子，并以第二速度将测试图案数据串行输出到外部与第一速度不同。

109. 发明授权

US07536618B2 Wide frequency range signal generator and method, and integrated circuit test system using same 有权
标题翻译：宽频率范围信号发生器及方法，集成电路测试系统采用相同方式
公开(公告)号：US07536618B2
公开(公告)日：2009-05-19
申请号：US11442515
申请日：2006-05-25
申请人： Greg Rausch , Rob Rabe , Jake Klier
发明人： Greg Rausch , Rob Rabe , Jake Klier
IPC分类号： G01R31/28
CPC分类号： G01R31/31922 , G06F1/08 , G11C29/56 , G11C29/56012 , H03K23/002
摘要： A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a toggling flip-flop. The frequency of the output clock signal is adjusted by selecting the flip-flop to which the input clock signal is coupled. Retimer flip-flops may be coupled between adjacent flip-flips to resynchronize the signal being coupled through the flip-flops. Each of the retimer flip-flops receives a respective signal from the output of an upstream flip-flop at its data input, and it receives the input clock signal at its clock input. The flip-flop then applies the signal to a downstream flip-flop in synchronism with the input clock signal. The final two flip-flops through which the input signal is coupled may be preset to various states to set the phase of the output clock signal to one of four phases.
摘要翻译：信号发生器通过将输入时钟信号通过多个分频器电路产生输出时钟信号，每个分频器电路由触发触发器形成。通过选择耦合输入时钟信号的触发器来调整输出时钟信号的频率。重定时器触发器可以耦合在相邻的翻转翻转之间，以重新同步通过触发器耦合的信号。每个重定时器触发器在其数据输入处从上游触发器的输出接收相应的信号，并且在其时钟输入端接收输入时钟信号。然后触发器与输入时钟信号同步地将信号施加到下游触发器。输入信号耦合的最后两个触发器可以预设为各种状态，以将输出时钟信号的相位设置为四相中的一个。

110. 发明申请

US20090125769A1 ON-CHIP CIRCUIT FOR TRANSITION DELAY FAULT TEST PATTERN GENERATION WITH LAUNCH OFF SHIFT 有权
标题翻译：用于转换延迟故障测试模式的片上电路与启动关闭移位
公开(公告)号：US20090125769A1
公开(公告)日：2009-05-14
申请号：US11939573
申请日：2007-11-14
申请人： Thai-Minh Nguyen , William Shen , David Vinke , Christopher Coleman
发明人： Thai-Minh Nguyen , William Shen , David Vinke , Christopher Coleman
IPC分类号： G06F11/25
CPC分类号： G01R31/318594 , G01R31/318552 , G11C29/10 , G11C29/56 , G11C29/56004 , G11C29/56012 , G11C2029/3602
摘要： A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a launch clock pulse and a capture clock pulse from the test clock pulses immediately after receiving a predetermined number of the test clock pulses immediately following the trigger pulse. A delayed scan enable output generates a delayed scan enable signal that transitions from the first state to the second state between a leading edge of the launch clock pulse and a leading edge of the capture clock pulse.
摘要翻译：时钟脉冲控制器包括用于接收测试时钟脉冲的测试时钟脉冲输入。扫描使能输入接收具有第一状态和第二状态的扫描使能信号。触发脉冲输入接收触发脉冲。时钟脉冲输出在接收到紧跟在触发脉冲之后的预定数量的测试时钟脉冲之后立即从测试时钟脉冲产生启动时钟脉冲和捕获时钟脉冲。延迟扫描使能输出产生延迟的扫描使能信号，其在启动时钟脉冲的前沿和捕获时钟脉冲的前沿之间从第一状态转换到第二状态。

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