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1. 发明授权

US07777513B2 Power supply voltage detection circuit and semiconductor integrated circuit device 失效
标题翻译：电源电压检测电路和半导体集成电路器件
公开(公告)号：US07777513B2
公开(公告)日：2010-08-17
申请号：US12213512
申请日：2008-06-20
申请人： Manabu Kitabatake , Yuji Tada , Kouji Naganawa , Tsuyoshi Hirakawa , Ichiro Mizuguchi
发明人： Manabu Kitabatake , Yuji Tada , Kouji Naganawa , Tsuyoshi Hirakawa , Ichiro Mizuguchi
IPC分类号： G01R31/26
CPC分类号： G01R31/31726 , G11C29/1201 , G11C29/12015 , G11C29/14 , G11C29/48 , G11C29/50012 , G11C29/56012 , G11C2029/0401 , G11C2029/5602 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device includes a first chip, a second chip to transmit and receive data to and from the first chip, and a through circuit provided in the first chip to transfer a clock signal and a test signal to the second chip. The clock signal and the test signal is inputted from an external device. The through circuit adjusts timing relation between the clock signal and the test signal based on a timing adjust signal. The timing adjust signal is inputted from the external device.
摘要翻译：半导体集成电路器件包括第一芯片，向第一芯片发送数据和从第一芯片接收数据的第二芯片，以及设置在第一芯片中的通过电路，将时钟信号和测试信号传送到第二芯片。时钟信号和测试信号从外部设备输入。通过电路基于定时调整信号调整时钟信号和测试信号之间的时序关系。定时调整信号从外部设备输入。

2. 发明申请

US20090015286A1 Power supply voltage detection circuit and semiconductor integrated circuit device 失效
标题翻译：电源电压检测电路和半导体集成电路器件
公开(公告)号：US20090015286A1
公开(公告)日：2009-01-15
申请号：US12213512
申请日：2008-06-20
申请人： Manabu Kitabatake , Yuji Tada , Kouji Naganawa , Tsuyoshi Hirakawa , Ichiro Mizuguchi
发明人： Manabu Kitabatake , Yuji Tada , Kouji Naganawa , Tsuyoshi Hirakawa , Ichiro Mizuguchi
IPC分类号： G01R31/26
CPC分类号： G01R31/31726 , G11C29/1201 , G11C29/12015 , G11C29/14 , G11C29/48 , G11C29/50012 , G11C29/56012 , G11C2029/0401 , G11C2029/5602 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit device includes a first chip, a second chip to transmit and receive data to and from the first chip, and a through circuit provided in the first chip to transfer a clock signal and a test signal to the second chip. The clock signal and the test signal is inputted from an external device. The through circuit adjusts timing relation between the clock signal and the test signal based on a timing adjust signal. The timing adjust signal is inputted from the external device.
摘要翻译：半导体集成电路器件包括第一芯片，向第一芯片发送数据和从第一芯片接收数据的第二芯片，以及设置在第一芯片中的通过电路，将时钟信号和测试信号传送到第二芯片。时钟信号和测试信号从外部设备输入。通过电路基于定时调整信号调整时钟信号和测试信号之间的时序关系。定时调整信号从外部设备输入。

3. 发明授权

US08436469B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08436469B2
公开(公告)日：2013-05-07
申请号：US13490871
申请日：2012-06-07
申请人： Yuji Tada , Tsuyoshi Hirakawa , Hironori Nakamura , Takayuki Kurokawa
发明人： Yuji Tada , Tsuyoshi Hirakawa , Hironori Nakamura , Takayuki Kurokawa
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/485 , H01L23/3121 , H01L23/525 , H01L23/552 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device, includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a predetermined layer and another one of the ground lines extending from the one of the ground lines toward another direction in the predetermined layer, a first pad on the multi-layer wiring layer, a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first and second pads, and an insulation film covering the redistribution line, the redistribution line extending above the ground lines along the one of the ground lines and not extending along the another one of the ground lines. The insulation film includes a hole exposing the second pad above an end portion of the one of the ground lines.
摘要翻译：一种半导体器件，包括：衬底，形成在衬底上的多层布线层，并且包括信号线和在信号线上方延伸的接地线，其中一条接地线朝向预定层的方向延伸，另一条所述接地线从所述接地线中的一条向所述预定层中的另一方向延伸，所述多层布线层上的第一焊盘，形成在所述多层布线层上的再分布层，包括第二焊盘，再分布线耦合所述第一和第二焊盘以及覆盖所述再分配线的绝缘膜，所述再分配线沿着所述接地线之一延伸到所述接地线之上，并且不沿着所述另一个所述接地线延伸。绝缘膜包括在第一接地线之一的端部上方露出第二焊盘的孔。

4. 发明授权

US08405219B2 Semiconductor device 有权
公开(公告)号：US08405219B2
公开(公告)日：2013-03-26
申请号：US13490871
申请日：2012-06-07
申请人： Yuji Tada , Tsuyoshi Hirakawa , Hironori Nakamura , Takayuki Kurokawa
发明人： Yuji Tada , Tsuyoshi Hirakawa , Hironori Nakamura , Takayuki Kurokawa
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
摘要： A semiconductor device, includes a substrate, a multi-layer wiring layer formed on the substrate, and including a signal line and ground lines extending above the signal line, one of the ground lines extending toward a direction in a predetermined layer and another one of the ground lines extending from the one of the ground lines toward another direction in the predetermined layer, a first pad on the multi-layer wiring layer, a redistribution layer formed on the multi-layer wiring layer, including a second pad, a redistribution line coupling the first and second pads, and an insulation film covering the redistribution line, the redistribution line extending above the ground lines along the one of the ground lines and not extending along the another one of the ground lines. The insulation film includes a hole exposing the second pad above an end portion of the one of the ground lines.

5. 发明申请

US20110241216A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20110241216A1
公开(公告)日：2011-10-06
申请号：US12929968
申请日：2011-02-28
申请人： Yuji Tada , Tsuyoshi Hirakawa , Hironori Nakamura , Takayuki Kurokawa
发明人： Yuji Tada , Tsuyoshi Hirakawa , Hironori Nakamura , Takayuki Kurokawa
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L23/3121 , H01L23/525 , H01L23/552 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device includes a substrate over which a circuit is formed, a multi-layer wiring layer having a plurality of wiring layers formed over the substrate and a pad formed in a predetermined location of an uppermost layer of the wiring layers, a new pad provided in an appropriate location over the multi-layer wiring layer, and a redistribution layer provided with a redistribution line coupling the new pad and the pad. In the semiconductor device: the multi-layer wiring layer includes a signal line for transmitting an electric signal to the circuit and a ground line provided in a wiring layer between the redistribution line or the new pad and the circuit; the ground line is formed to correspond to a location where the new pad is assumed to be located and a route along which the redistribution line is assumed to be formed; and the redistribution line is formed along at least a portion of the ground line.
摘要翻译：半导体器件包括：形成电路的基板;在基板上形成有多个布线层的多层布线层和形成在布线层的最上层的预定位置的焊盘;提供新的焊盘在多层布线层上的适当位置，以及设置有耦合新衬垫和衬垫的再分配线的再分配层。在半导体器件中：多层布线层包括用于向电路发送电信号的信号线和设置在再分配线或新焊盘和电路之间的布线层中的接地线; 地线被形成为对应于假定要设置新垫的位置，以及假定形成再分配线的路径; 并且再分配线沿着地线的至少一部分形成。

6. 发明授权

US08237287B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08237287B2
公开(公告)日：2012-08-07
申请号：US12929968
申请日：2011-02-28
申请人： Yuji Tada , Tsuyoshi Hirakawa , Hironori Nakamura , Takayuki Kurokawa
发明人： Yuji Tada , Tsuyoshi Hirakawa , Hironori Nakamura , Takayuki Kurokawa
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/485 , H01L23/3121 , H01L23/525 , H01L23/552 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06527 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device includes a substrate over which a circuit is formed, a multi-layer wiring layer having a plurality of wiring layers formed over the substrate and a pad formed in a predetermined location of an uppermost layer of the wiring layers, a new pad provided in an appropriate location over the multi-layer wiring layer, and a redistribution layer provided with a redistribution line coupling the new pad and the pad. In the semiconductor device: the multi-layer wiring layer includes a signal line for transmitting an electric signal to the circuit and a ground line provided in a wiring layer between the redistribution line or the new pad and the circuit; the ground line is formed to correspond to a location where the new pad is assumed to be located and a route along which the redistribution line is assumed to be formed; and the redistribution line is formed along at least a portion of the ground line.
摘要翻译：半导体器件包括：形成电路的基板;在基板上形成有多个布线层的多层布线层和形成在布线层的最上层的预定位置的焊盘;提供新的焊盘在多层布线层上的适当位置，以及设置有耦合新衬垫和衬垫的再分配线的再分配层。在半导体器件中：多层布线层包括用于向电路发送电信号的信号线和设置在再分配线或新焊盘和电路之间的布线层中的接地线; 地线被形成为对应于假定要设置新垫的位置，以及假定形成再分配线的路径; 并且再分配线沿着地线的至少一部分形成。

7. 发明申请

US20120299818A1 MEDICAL INFORMATION DISPLAY APPARATUS, OPERATION METHOD OF THE SAME AND MEDICAL INFORMATION DISPLAY PROGRAM 审中-公开
标题翻译：医疗信息显示装置，其操作方法和医疗信息显示程序
公开(公告)号：US20120299818A1
公开(公告)日：2012-11-29
申请号：US13480337
申请日：2012-05-24
申请人： Yuanzhong Li , Tsuyoshi Hirakawa , Takuya Ebina , Jun Masumoto , Hajime Shirasaka
发明人： Yuanzhong Li , Tsuyoshi Hirakawa , Takuya Ebina , Jun Masumoto , Hajime Shirasaka
IPC分类号： G06F3/01
CPC分类号： G06F19/321 , G06F3/0484 , G06F3/04855 , G06F2203/04806 , G16H10/60
摘要： One of hierarchical images constituted by an appearance image representing an appearance of a subject body and a plurality of gradually magnified anatomy images schematically representing anatomical structures present inside of the body is displayed on a display unit. If a structure present at a desired position in the displayed image on the display unit specified by the specification input corresponds to a target examined region, the displayed image is switched to the examination information associated with the target examined region to display the examination information.
摘要翻译：在显示单元上显示由表示被摄体的外观的图像图像构成的分层图像和示意性地表示身体内部的解剖结构的多个逐渐放大的解剖图像。如果存在于由指定输入指定的显示单元上的显示图像中的期望位置处的结构对应于目标检查区域，则将显示的图像切换到与目标检查区域相关联的检查信息以显示检查信息。

8. 发明授权

US5943260A Method for high-speed programming of a nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件的高速编程方法
公开(公告)号：US5943260A
公开(公告)日：1999-08-24
申请号：US27215
申请日：1998-02-20
申请人： Tsuyoshi Hirakawa
发明人： Tsuyoshi Hirakawa
IPC分类号： G11C16/02 , G11C11/56 , G11C7/00
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C2211/5621
摘要： A flash EEPROM has a plurality of multi-valued memory cells grouped in a plurality blocks or pages for parallel programming. If the data values for parallel programming include data "10" for a first group, data "01" for a second group and data "00" for a third group of memory cells in a page, a first voltage corresponding to data "10" is applied to the first through third groups, a second voltage corresponding to data "01" is applied to the second and the third groups, and a third voltage corresponding to data "00" is applied to the third groups, thereby reducing the programming time length for the parallel programming.
摘要翻译：闪存EEPROM具有分组在多个块中的多个多值存储器单元，用于并行编程。如果用于并行编程的数据值包括第一组的数据“10”，则第二组的数据“01”和页面中的第三组存储器单元的数据“00”，对应于数据“10”的第一电压被施加到第一至第三组，对应于数据“01”的第二电压被施加到第二组和第三组，并且对应于数据“00”的第三电压被施加到第三组，从而减少编程时间并行编程的长度。

9. 发明授权

US07965568B2 Semiconductor integrated circuit device and method of testing same 失效
标题翻译：半导体集成电路器件及其测试方法
公开(公告)号：US07965568B2
公开(公告)日：2011-06-21
申请号：US12350546
申请日：2009-01-08
申请人： Kenichi Ushikoshi , Nobutoshi Tsunesada , Tsuyoshi Hirakawa , Noriaki Komatsu
发明人： Kenichi Ushikoshi , Nobutoshi Tsunesada , Tsuyoshi Hirakawa , Noriaki Komatsu
IPC分类号： G11C7/00
CPC分类号： G11C29/14 , G11C11/401 , G11C29/12015 , G11C29/56012
摘要： A semiconductor integrated circuit device includes a first chip that is directly accessible from outside, a second chip that transmits and receives data to and from the first chip, the second chip being not directly accessible from outside, and a through circuit that is provided in the first chip and transmits first and second test signals input from an external device to the second chip, wherein the through circuit includes a first signal transmission path to generate a first signal by synchronizing the first test signal to a clock signal input from the external device and to output it to the second chip and a second signal transmission path to generate a second signal by synchronizing the second test signal to a test clock signal input from the external device and to output it to the second chip.
摘要翻译：半导体集成电路器件包括可从外部直接访问的第一芯片，向第一芯片发送数据和从第一芯片接收数据的第二芯片，第二芯片不能从外部直接访问;以及贯穿电路，其设置在第一芯片，并将从外部设备输入的第一和第二测试信号传输到第二芯片，其中所述通过电路包括第一信号传输路径，以通过将所述第一测试信号与从所述外部设备输入的时钟信号同步来产生第一信号;以及将其输出到第二芯片和第二信号传输路径，以通过将第二测试信号与从外部设备输入的测试时钟信号同步并将其输出到第二芯片来产生第二信号。

10. 发明申请

US20090190417A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF TESTING SAME 失效
标题翻译：半导体集成电路装置及其测试方法
公开(公告)号：US20090190417A1
公开(公告)日：2009-07-30
申请号：US12350546
申请日：2009-01-08
申请人： KENICHI USHIKOSHI , Nobutoshi Tsunesada , Tsuyoshi Hirakawa , Noriaki Komatsu
发明人： KENICHI USHIKOSHI , Nobutoshi Tsunesada , Tsuyoshi Hirakawa , Noriaki Komatsu
IPC分类号： G11C7/00 , H03L7/00 , G11C8/18 , G01R31/26
CPC分类号： G11C29/14 , G11C11/401 , G11C29/12015 , G11C29/56012
摘要： A semiconductor integrated circuit device includes a first chip that is directly accessible from outside, a second chip that transmits and receives data to and from the first chip, the second chip being not directly accessible from outside, and a through circuit that is provided in the first chip and transmits first and second test signals input from an external device to the second chip, wherein the through circuit includes a first signal transmission path to generate a first signal by synchronizing the first test signal to a clock signal input from the external device and to output it to the second chip and a second signal transmission path to generate a second signal by synchronizing the second test signal to a test clock signal input from the external device and to output it to the second chip.
摘要翻译：半导体集成电路器件包括可从外部直接访问的第一芯片，向第一芯片发送数据和从第一芯片接收数据的第二芯片，第二芯片不能从外部直接访问;以及贯穿电路，其设置在第一芯片，并将从外部设备输入的第一和第二测试信号传输到第二芯片，其中所述通过电路包括第一信号传输路径，以通过将所述第一测试信号与从所述外部设备输入的时钟信号同步来产生第一信号;以及将其输出到第二芯片和第二信号传输路径，以通过将第二测试信号与从外部设备输入的测试时钟信号同步并将其输出到第二芯片来产生第二信号。

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