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1. 发明申请

US20120079330A1 TEST DEVICE AND TEST METHOD FOR RESISTIVE RANDOM ACCESS MEMORY AND RESISTIVE RANDOM ACCESS MEMORY DEVICE 有权
标题翻译：电阻随机访问存储器和电阻随机访问存储器件的测试装置和测试方法
公开(公告)号：US20120079330A1
公开(公告)日：2012-03-29
申请号：US13238479
申请日：2011-09-21
申请人： Kazuaki KAWAGUCHI , Kazushige Kanda
发明人： Kazuaki KAWAGUCHI , Kazushige Kanda
IPC分类号： G11C29/08 , G06F11/273
CPC分类号： G11C29/56 , G11C11/16 , G11C13/00 , G11C29/50012 , G11C29/56012
摘要： According to the embodiments, a first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted.
摘要翻译：根据实施例，在恒定周期改变的第一写入使能信号和在字线的激活/停止控制和位线的激活/去激活控制之间的限制时间的时间部分发生变化的第二写使能信号是多个核心控制信号，其中核心控制信号改变的时间间隔基于输入的第一写入使能信号和第二写入使能信号而局部地短于第一写入使能信号的周期并且通过使用所生成的核心控制信号来执行电阻性随机存取存储器的操作验证，从而局部地和任意地调整任意测试周期中的周期时间。

2. 发明申请

US20110019492A1 TEST DEVICE AND TEST METHOD FOR RESISTIVE RANDOM ACCESS MEMORY AND RESISTIVE RANDOM ACCESS MEMORY DEVICE 审中-公开
标题翻译：电阻随机访问存储器和电阻随机访问存储器件的测试装置和测试方法
公开(公告)号：US20110019492A1
公开(公告)日：2011-01-27
申请号：US12752646
申请日：2010-04-01
申请人： Kazuaki KAWAGUCHI , Kazushige KANDA
发明人： Kazuaki KAWAGUCHI , Kazushige KANDA
IPC分类号： G11C29/00 , G11C11/00
CPC分类号： G11C29/56 , G11C19/28 , G11C29/56012
摘要： A first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted.
摘要翻译：输入第一写入使能信号，其以检查字线的激活/去激活控制和位线的激活/去激活控制之间的限制时间的时间部分上变化的恒定周期和第二写使能信号进行改变，产生多个核心控制信号，其中核心控制信号改变的时间间隔基于输入的第一写入使能信号和第二写入使能信号而局部地短于第一写入使能信号的周期，并且通过使用所生成的核心控制信号来执行电阻式随机存取存储器的操作验证，由此本地和任意调整任意测试周期中的周期时间。

3. 发明申请

US20080101130A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080101130A1
公开(公告)日：2008-05-01
申请号：US11928970
申请日：2007-10-30
申请人： Kazuaki KAWAGUCHI , Naoaki Kanagawa
发明人： Kazuaki KAWAGUCHI , Naoaki Kanagawa
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1078 , G11C7/10 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1087 , G11C2207/105
摘要： A semiconductor device includes plural memory cell blocks, each having a memory cell array of plural memory cells. Plural control circuits are provided in correspondence with each of the memory cell blocks, for writing information to the memory cell blocks and for reading information written in the memory cell blocks. Plural input/output terminals are for inputting the information to be written and for outputting the information to be read. Plural multiplexers are provided in correspondence with each of the input/output terminals, for conveying the information to be written from the input/output terminals and for conveying the information to be read to the input/output terminals. A bidirectional transfer type buffer is connected to each connection line between the control circuits and the multiplexers, for selectively conveying information from the control circuits to each of the multiplexers and for selectively conveying information from the multiplexers to each of the control circuits.
摘要翻译：半导体器件包括多个存储单元块，每个存储单元块具有多个存储单元的存储单元阵列。与每个存储单元块相对应地提供多个控制电路，用于将信息写入存储单元块并读取写入存储单元块中的信息。多个输入/输出端子用于输入要写入的信息并输出要读取的信息。与每个输入/输出端相对应地提供多路复用器，用于传送要从输入/输出端子写入的信息，并将要读取的信息传送到输入/输出端子。双向传输型缓冲器连接到控制电路和多路复用器之间的每个连接线，用于选择性地将信息从控制电路传送到多路复用器中的每一个，并用于选择性地将信息从多路复用器传送到每个控制电路。

4. 发明申请

US20110235392A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110235392A1
公开(公告)日：2011-09-29
申请号：US12885881
申请日：2010-09-20
申请人： Kazuaki KAWAGUCHI , Takahiko SASAKI , Tomonori KUROSAWA
发明人： Kazuaki KAWAGUCHI , Takahiko SASAKI , Tomonori KUROSAWA
IPC分类号： G11C11/21
CPC分类号： G11C8/08 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/0061 , G11C2013/0083
摘要： According to one embodiment, a nonvolatile semiconductor storage device having a plurality of operation modes, includes: a plurality of first lines; a plurality of second lines; a plurality of memory cells; a first selection unit that charges the first line to a first selection voltage; and a second selection unit that charges a second line to an unselection voltage and discharges the second line to a second selection voltage after the first line is charged to the first selection voltage by the first selection unit, wherein the second selection unit adjusts at least one of a level of the second selection voltage to which the second line to be selected is to be discharged and a time constant when discharging the second line to be selected, in accordance with an operation mode in which the nonvolatile semiconductor storage device operates among the plurality of operation modes.
摘要翻译：根据一个实施例，具有多个操作模式的非易失性半导体存储装置包括：多个第一线; 多条第二线; 多个存储单元; 第一选择单元，将第一行充电到第一选择电压; 以及第二选择单元，其在第一线路被第一选择单元充电到第一选择电压之后，将第二线路充电到非选择电压并将第二线路放电到第二选择电压，其中第二选择单元调整至少一个根据非易失性半导体存储装置在多个操作中的操作模式，要选择要选择的第二线路的第二选择电压的电平和放电要选择的第二线路的时间常数的操作模式。

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