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101. 发明申请

US20060188052A1 Data transmission controller and sampling frequency converter 有权
公开(公告)号：US20060188052A1
公开(公告)日：2006-08-24
申请号：US11355638
申请日：2006-02-15
申请人： Takayoshi Mochizuki , Naotoshi Nishioka
发明人： Takayoshi Mochizuki , Naotoshi Nishioka
IPC分类号： H04L7/00
CPC分类号： H04H20/95 , G06F5/12 , G06F2205/061 , H04J3/062 , H04L7/0041 , H04L7/005
摘要： In a data transmission controller apparatus, a first-in first-out storage stores newly inputted data in response to a write request signal, and reads and outputs the stored data which has been stored earliest in response to a read request signal. A remaining data amount detection portion detects a remaining data amount of the stored data which remain in the first-in first-out storage. A variable frequency oscillating portion generates an enable signal at a time rate according to frequency control information so as to enable generation of the write request signal or read request signal. A frequency control portion corrects the frequency control information so as to return the remaining data amount to an appropriate value when the remaining data amount detected by the remaining data amount detection portion varies away from the appropriate value toward an upper limit value or varies away from the appropriate value toward a lower limit value.

102. 发明授权

US06819732B1 Asynchronous sample rate estimation using reciprocal frequency error minimization 有权
标题翻译：使用倒数频率误差最小化的异步采样率估计
公开(公告)号：US06819732B1
公开(公告)日：2004-11-16
申请号：US09644141
申请日：2000-08-22
申请人： Thomas C. Savell
发明人： Thomas C. Savell
IPC分类号： H04L700
CPC分类号： G06F5/12 , G06F2205/061 , G06F2205/126 , H04L25/0262
摘要： An asynchronous sample rate estimator and a method for generating a rate estimate to track an asynchronous input sampled signal is disclosed. The present invention achieves lock quickly and maintains an optimum input buffer configuration and enhanced signal fidelity by responding quickly and accurately to changes in the incoming frequency. An asynchronous sample rate estimator receives and determines a measured sample period of an asynchronous input signal. Furthermore, a reciprocal frequency error signal and a current rate estimate signal are used to generate a rate estimate for tracking the read pointer to the write pointer of a FIFO buffer, as well as a phase correction signal for centering the write pointer in the FIFO buffer. An asynchronous sample rate estimator might also include an error gain generator for providing an error gain and a lock detector for indicating whether the system has achieved a locked condition.
摘要翻译：公开了异步采样率估计器和用于产生跟踪异步输入采样信号的速率估计的方法。本发明通过快速准确地响应输入频率的变化来快速实现锁定并保持最佳输入缓冲器配置和增强的信号保真度。异步采样率估计器接收并确定异步输入信号的测量采样周期。此外，使用互逆频率误差信号和当前速率估计信号来产生用于跟踪到FIFO缓冲器的写指针的读指针的速率估计，以及用于使写指针在FIFO缓冲器中居中的相位校正信号。异步采样率估计器还可以包括用于提供误差增益的误差增益发生器和用于指示系统是否已经达到锁定状态的锁定检测器。

103. 发明申请

US20030227988A1 Jitter and wander reduction apparatus 有权
标题翻译：抖动和漫游减少装置
公开(公告)号：US20030227988A1
公开(公告)日：2003-12-11
申请号：US10346550
申请日：2003-01-17
发明人： Ravi Subrahmanyan , Jeffrey W. Spires
IPC分类号： H04L007/00 , H04L025/00
CPC分类号： G06F5/12 , G06F2205/061 , H04J3/076
摘要： The present invention is for an apparatus that receives input data at a non-uniform first data rate carried by a system clock, and provides output data at a substantially uniform second data rate that is nominally equal to the first data rate and is also carried by the system clock. The system clock is faster than the first or second data rates and accordingly, a write enable signal controls the input data that is written into a saturating elastic store and a read enable signal controls the reading and output of data from the saturating elastic store. The saturating elastic store includes a plurality of storage locations and provides a storage fill level indicative of the amount of storage locations currently holding data. A digital filter receives the storage fill level and filters the storage fill level to provide a control word to a digitally controlled read enable signal generator. The digitally controlled read enable signal generator provides a read enable signal that is nominally the second data rate and that can be varied about the nominal second data rate in response to the control word. The digitally controlled read enable signal generator is able to vary the read enable signal rate by providing a plurality of stuff bit opportunities interspersed between the read enable signals. Some of these stuff bit opportunities are filled to set the read enable signal rate at the nominal second data rate value. By filling or not filling the stuff bit opportunities, the read enable signal rate can be adjusted over a narrow band of frequencies.
摘要翻译：本发明是用于以由系统时钟承载的不均匀的第一数据速率接收输入数据的装置，并且以基本均匀的第二数据速率提供输出数据，该数据速率名义上等于第一数据速率，并且还由系统时钟。系统时钟比第一或第二数据速率更快，因此，写入使能信号控制写入饱和弹性存储器的输入数据，并且读使能信号控制从饱和弹性存储器读取和输出数据。饱和弹性存储器包括多个存储位置，并且提供指示当前保存数据的存储位置的量的存储填充水平。数字滤波器接收存储器填充电平并对存储器填充电平进行滤波以向数字控制的读使能信号发生器提供控制字。数字控制的读使能信号发生器提供了名义上为第二数据速率的读使能信号，并且响应于控制字可以改变关于标称第二数据速率的读使能信号。数字控制读使能信号发生器能够通过提供散布在读使能信号之间的多个填充位机会来改变读使能信号速率。填充这些填充位的一些机会，以将读取使能信号速率设置在标称的第二数据速率值。通过填充或不填充填充位机会，可以在窄频带上调整读取使能信号速率。

104. 发明授权

US06519722B1 Method and apparatus for controlling the read clock signal rate of a first-in first-out (FIFO) data memory 有权
标题翻译：用于控制先进先出（FIFO）数据存储器的读时钟信号速率的方法和装置
公开(公告)号：US06519722B1
公开(公告)日：2003-02-11
申请号：US09533565
申请日：2000-03-22
申请人： David Wiggins
发明人： David Wiggins
IPC分类号： G06F1100
CPC分类号： G06F5/06 , G06F2205/061 , H04J3/076
摘要： A method and apparatus for controlling the read clock signal rate of a First-In First-Out data memory is provided. A control signal for controlling the read clock signal rate is derived from an error signal, wherein the level of data contained in the FIFO is used to generate the error signal. The control signal includes an integral element, which comprises the error signal, scaled by a first paramater and integrated over time, and a proportional element, which comprises the error signal scaled by a second parameter. In accordance with the invention, at least one of the first and second scaling parameters is varied in accordance with the absolute error signal level. In a preferred embodiment, the or each parameter is varied as an exponential function of the absolute error signal level. This results in the bandwidth of the apparatus varying exponentially with the absolute error signal level. The dynamic or adaptive nature of the bandwidth enables the apparatus to provide an output data stream with relatively low wander or jitter under normal operating conditions while preventing data loss due to FIFO overflow or underflow in extreme operating conditions. The invention has particular application in the desynchronization of plesiochronous data elements from a synchronous transmission format in a telecommunications network system.
摘要翻译：提供了一种用于控制先进先出数据存储器的读取时钟信号速率的方法和装置。从误差信号导出用于控制读时钟信号速率的控制信号，其中包含在FIFO中的数据电平用于产生误差信号。控制信号包括积分元件，其包括由第一参数进行了缩放并随时间积分的误差信号，以及包括由第二参数缩放的误差信号的比例元件。根据本发明，第一和第二缩放参数中的至少一个根据绝对误差信号电平而变化。在优选实施例中，该或每个参数被改变为绝对误差信号电平的指数函数。这导致设备的带宽随绝对误差信号电平呈指数变化。带宽的动态或自适应性能使装置在正常操作条件下提供具有相对较低漂移或抖动的输出数据流，同时防止在极端操作条件下FIFO溢出或下溢引起的数据丢失。本发明在电信网络系统中从同步传输格式的同步数据元素的同步化中具有特别的应用。

105. 发明申请

US20030005348A1 Clock reproducing method and receiving clock producing apparatus 失效
标题翻译：时钟再现方法和接收时钟产生装置
公开(公告)号：US20030005348A1
公开(公告)日：2003-01-02
申请号：US10164311
申请日：2002-06-07
申请人： NEC CORPORATION
发明人： Jun Furukawa , Yoshiaki Nozawa , Yasuhiro Arasawa
IPC分类号： G06F001/04
CPC分类号： G06F5/12 , G06F2205/061 , H04N21/4305 , H04N21/64307
摘要： In a receiving clock reproducing method, an estimated value of delay time fluctuation of a received signal is estimated at intervals defined by transmitting clock included in the received signal. To estimate the estimated value, an oscillator counter counts pulses of a reference clock supplied from an independent oscillator while a reading counter counts pulses of the receiving clock. The estimated value is used to control a voltage controlled oscillator for producing the receiving clock.
摘要翻译：在接收时钟再现方法中，以包括在接收信号中的发送时钟定义的间隔估计接收信号的延迟时间波动的估计值。为了估计估计值，振荡器计数器计数从独立振荡器提供的参考时钟的脉冲，而读取计数器计数接收时钟的脉冲。估计值用于控制用于产生接收时钟的压控振荡器。

106. 发明申请

US20020172310A1 Jitter attenuator fifo overflow-underflow protection using digital-phase locked loop's bandwidth adaptation 审中-公开
标题翻译：抖动衰减器使用数字锁相环的带宽自适应进行上溢溢出保护
公开(公告)号：US20020172310A1
公开(公告)日：2002-11-21
申请号：US09860906
申请日：2001-05-18
发明人： Manop Thamsirianunt , Tony Wong
IPC分类号： H04L007/00
CPC分类号： G06F5/12 , G06F2205/061 , H03L7/107 , H04J3/0626
摘要： The present invention provides a jitter attenuator that has a phase locked loop (PLL), the PLL having a programmable bandwidth setting. The jitter attenuator also has a first-in/first-out (FIFO) buffer for storing data, a write clock for providing a write pulse to the FIFO, a read clock for providing a read pulse to the FIFO, and a pointer generator for controlling the programmable bandwidth in response to the difference between the frequencies of the write and read clocks.
摘要翻译：本发明提供了具有锁相环（PLL）的抖动衰减器，PLL具有可编程带宽设置。抖动衰减器还具有用于存储数据的先进先出（FIFO）缓冲器，用于向FIFO提供写脉冲的写时钟，向FIFO提供读脉冲的读时钟，以及用于响应于写和时钟的频率之间的差异来控制可编程带宽。

107. 发明授权

US06356611B1 Bit rate control interface for the recording and/or reading of digital data 失效
标题翻译：用于记录和/或读取数字数据的比特率控制接口
公开(公告)号：US06356611B1
公开(公告)日：2002-03-12
申请号：US09044443
申请日：1998-03-19
申请人： Claude Chapel , Jean-Yves Quintard , François Bourdon
发明人： Claude Chapel , Jean-Yves Quintard , François Bourdon
IPC分类号： H04L2540
CPC分类号： G06F5/06 , G06F2205/061
摘要： A control interface for the bit rate of digital data to be recorded as well as a control interface for the bit rate of digital data emanating from a reading device, particularly when the digital data constitutes a high bit rate uninterrupted data stream such as a video data stream in the MPEG II format. Each control interface comprises a memory circuit for storing the data to be recorded or to be read and a device for storing the data to be recorded or read in the memory circuit so as to fill the memory circuit to a predetermined level. The storing device includes a gauge for generating an information item giving the fill level of the memory.
摘要翻译：用于要记录的数字数据的比特率的控制接口以及用于从读取装置发出的数字数据的比特率的控制接口，特别是当数字数据构成诸如视频数据的高比特率不间断数据流时以MPEG II格式流。每个控制接口包括用于存储待记录或待读取的数据的存储器电路和用于存储要在存储器电路中记录或读取的数据以将存储器电路填充到预定水平的装置。存储装置包括用于生成给出存储器的填充级别的信息项的计量器。

108. 发明授权

US06263036B1 Asynchronous signal input apparatus and sampling frequency conversion apparatus 失效
标题翻译：异步信号输入装置和采样变频装置
公开(公告)号：US06263036B1
公开(公告)日：2001-07-17
申请号：US09124752
申请日：1998-07-29
申请人： Yusuke Yamamoto , Ichiro Futohashi , Yasuyuki Muraki
发明人： Yusuke Yamamoto , Ichiro Futohashi , Yasuyuki Muraki
IPC分类号： H04L2500
CPC分类号： G06F5/14 , G06F2205/061 , H03H17/0628
摘要： An asynchronous signal input apparatus includes a memory device which writes data that are input at a predetermined frequency, in response to a write signal, and reads data in response to a read signal. A data quantity measuring device measures a data quantity representing a quantity of data stored in the memory device. A read signal generating device generates the read signal at a frequency that varies depending upon the measured data quantity. A sampling frequency conversion apparatus comprises the memory device, data quantity measuring device, and read signal generating device employed in the asynchronous signal input apparatus. Further, the read signal generating device includes a converter which performs non-linear conversion on the data quantity measured by the data quantity measuring device. An interpolation information producing device produces interpolation information to be used for data generated from the memory device, based on the data quantity to which the non-linear gain is given by the converter. An interpolation device interpolates data that are read from the memory device in response to the read signal, based on the produced interpolation information.
摘要翻译：异步信号输入装置包括响应于写信号写入以预定频率输入的数据的存储装置，并响应于读信号读取数据。数据量测量装置测量表示存储在存储装置中的数据量的数据量。读取信号产生装置以取决于测量数据量而变化的频率产生读取信号。采样频率转换装置包括在异步信号输入装置中采用的存储装置，数据量测量装置和读信号产生装置。此外，读信号生成装置包括对由数据量测量装置测量的数据量执行非线性转换的转换器。内插信息产生装置基于由转换器给出非线性增益的数据量，产生用于从存储装置生成的数据的内插信息。内插装置根据所生成的插值信息，内插根据读取信号从存储装置读出的数据。

109. 发明授权

US6057789A Re-synchronization of independently-clocked audio streams by dynamically switching among 3 ratios for sampling-rate-conversion 有权
标题翻译：通过在3个比率之间动态切换采样率转换，重新同步独立时钟的音频流
公开(公告)号：US6057789A
公开(公告)日：2000-05-02
申请号：US182348
申请日：1998-10-29
申请人： Tao Lin
发明人： Tao Lin
IPC分类号： G06F5/10 , H03M7/00 , G06F7/10
CPC分类号： G06F5/10 , G06F2205/061
摘要： A sample-rate converter has a FIFO for buffering input samples. The FIFO is written with an input sample by an input clock synchronized to the input audio stream. The samples are read from the FIFO by a derived clock. The derived clock is generated from an output clock using a nominal ratio of Q/P. Read and write counters for the FIFO are compared. When the write counter is ahead of the read counter by exactly a target amount the derived clock is a ratio of Q/P of the output clock. When the write counter is ahead of the read counter by more than the target, the read rate is increased by accelerating the derived clock to a ratio of (Q+1)/P. When the write counter is ahead of the read counter by less than the target amount, the read rate is decreased by slowing the derived clock to a ratio of (Q-1)/P. An accumulator generates the derived clock by adding Q, Q+1, or Q-1 for each output-clock pulse. Each derived-clock pulse reduces the accumulator by P. The accumulator value is used to select one group of L coefficients in a set of P groups to apply to a convolution FIR filter that generates the output sample from L input samples stored from the FIFO in a shift register.
摘要翻译：采样率转换器具有用于缓冲输入采样的FIFO。 FIFO通过与输入音频流同步的输入时钟写入输入采样。通过派生时钟从FIFO读取样本。导出时钟是使用标称比例的Q / P从输出时钟生成的。比较FIFO的读写计数器。当写计数器在读计数器之前超过目标量时，导出时钟是输出时钟的Q / P比。当写计数器超过读取计数器超过目标时，通过将导出的时钟加速到（Q + 1）/ P的比率来增加读取速率。当写计数器在读取计数器之前小于目标量时，通过将导出的时钟减慢到（Q-1）/ P的比率来减小读取速率。累加器通过为每个输出时钟脉冲添加Q，Q + 1或Q-1来产生导出的时钟。每个派生时钟脉冲将累加器减少P.累加器值用于选择一组P组中的一组L系数，以应用于从FIFO中存储的L个输入样本生成输出样本的卷积FIR滤波器一个移位寄存器。

110. 发明授权

US6029234A Output synchronization method and apparatus in a memory system utilizing small buffer size 失效
标题翻译：使用小缓冲大小的存储系统中的输出同步方法和装置
公开(公告)号：US6029234A
公开(公告)日：2000-02-22
申请号：US763663
申请日：1996-12-11
申请人： Takashi Yamaguchi
发明人： Takashi Yamaguchi
IPC分类号： G06F5/12 , G06F5/06 , G06T1/60 , G06F13/00
CPC分类号： G06F5/06 , G06F2205/061
摘要： The present invention provides an output synchronization method and apparatus in which an appropriate amount of data can be stored in a buffer memory all the time by detecting a change in output speed of data outputted from the buffer memory and a large amount of data can be handled with a small buffer size. According to the present invention, a change in the output speed of data outputted from a buffer memory, from which data is read and outputted at a time when it is required after input data is stored, is measured, and data inputted to the buffer memory is controlled according to the change in the output speed.
摘要翻译：本发明提供了一种输出同步方法和装置，其中通过检测从缓冲存储器输出的数据的输出速度的变化，可以将适当量的数据一直存储在缓冲存储器中，并且可以处理大量的数据具有小的缓冲区大小。根据本发明，测量从存储输入数据之后需要读取和输出数据的缓冲存储器输出的数据的输出速度的变化，输入到缓冲存储器的数据根据输出速度的变化进行控制。

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