![Jitter and wander reduction apparatus](/abs-image/US/2003/12/11/US20030227988A1/abs.jpg.150x150.jpg)
基本信息:
- 专利标题: Jitter and wander reduction apparatus
- 专利标题(中):抖动和漫游减少装置
- 申请号:US10346550 申请日:2003-01-17
- 公开(公告)号:US20030227988A1 公开(公告)日:2003-12-11
- 发明人: Ravi Subrahmanyan , Jeffrey W. Spires
- 主分类号: H04L007/00
- IPC分类号: H04L007/00 ; H04L025/00
摘要:
The present invention is for an apparatus that receives input data at a non-uniform first data rate carried by a system clock, and provides output data at a substantially uniform second data rate that is nominally equal to the first data rate and is also carried by the system clock. The system clock is faster than the first or second data rates and accordingly, a write enable signal controls the input data that is written into a saturating elastic store and a read enable signal controls the reading and output of data from the saturating elastic store. The saturating elastic store includes a plurality of storage locations and provides a storage fill level indicative of the amount of storage locations currently holding data. A digital filter receives the storage fill level and filters the storage fill level to provide a control word to a digitally controlled read enable signal generator. The digitally controlled read enable signal generator provides a read enable signal that is nominally the second data rate and that can be varied about the nominal second data rate in response to the control word. The digitally controlled read enable signal generator is able to vary the read enable signal rate by providing a plurality of stuff bit opportunities interspersed between the read enable signals. Some of these stuff bit opportunities are filled to set the read enable signal rate at the nominal second data rate value. By filling or not filling the stuff bit opportunities, the read enable signal rate can be adjusted over a narrow band of frequencies.
摘要(中):
本发明是用于以由系统时钟承载的不均匀的第一数据速率接收输入数据的装置,并且以基本均匀的第二数据速率提供输出数据,该数据速率名义上等于第一数据速率,并且还由 系统时钟。 系统时钟比第一或第二数据速率更快,因此,写入使能信号控制写入饱和弹性存储器的输入数据,并且读使能信号控制从饱和弹性存储器读取和输出数据。 饱和弹性存储器包括多个存储位置,并且提供指示当前保存数据的存储位置的量的存储填充水平。 数字滤波器接收存储器填充电平并对存储器填充电平进行滤波以向数字控制的读使能信号发生器提供控制字。 数字控制的读使能信号发生器提供了名义上为第二数据速率的读使能信号,并且响应于控制字可以改变关于标称第二数据速率的读使能信号。 数字控制读使能信号发生器能够通过提供散布在读使能信号之间的多个填充位机会来改变读使能信号速率。 填充这些填充位的一些机会,以将读取使能信号速率设置在标称的第二数据速率值。 通过填充或不填充填充位机会,可以在窄频带上调整读取使能信号速率。
公开/授权文献:
- US07212599B2 Jitter and wander reduction apparatus 公开/授权日:2007-05-01