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101. 发明申请

US20080128712A1 RAISED STI STRUCTURE AND SUPERDAMASCENE TECHNIQUE FOR NMOSFET PERFORMANCE ENHANCEMENT WITH EMBEDDED SILICON CARBON 有权
标题翻译：用于具有嵌入式硅碳的NMOSFET性能增强的提高的结构和超级散射技术
公开(公告)号：US20080128712A1
公开(公告)日：2008-06-05
申请号：US12028191
申请日：2008-02-08
申请人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
发明人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
IPC分类号： H01L27/092 , H01L29/778
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译：通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区域施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C）用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积具有足够高的替代碳含量的Si：C固有地是非选择性的。

102. 发明授权

US07337420B2 Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models 有权
标题翻译：基于布局的调制方法和紧凑模型中氮化物衬垫应力效应的优化
公开(公告)号：US07337420B2
公开(公告)日：2008-02-26
申请号：US11193711
申请日：2005-07-29
申请人： Dureseti Chidambarrao , Donald L. Jordan , Judith H. McCullen , David M. Onsongo , Tina Wagner , Richard Q. Williams
发明人： Dureseti Chidambarrao , Donald L. Jordan , Judith H. McCullen , David M. Onsongo , Tina Wagner , Richard Q. Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5036 , H01L29/7843
摘要： System and method for compact model algorithms to accurately account for effects of layout-induced changes in nitride liner stress in semiconductor devices. The layout-sensitive compact model algorithms account for the impact of large layout variation on circuits by implementing algorithms for obtaining the correct stress response approximations and layout extraction algorithms for obtaining the correct geometric parameters that drive the stress response. In particular, these algorithms include specific information from search “buckets” that are directionally-oriented and include directionally-specific distance measurements for analyzing in detail the specific shape neighborhood of the semiconductor device. The algorithms are additionally adapted to enable the modeling and stress impact determination of a device having single stress liner film and dual-stress liners (two different liner films that abut at an interface).
摘要翻译：用于紧凑模型算法的系统和方法来准确地解释半导体器件中氮化物衬垫应力的布局引起的变化的影响。布局敏感的压缩模型算法通过实现用于获得正确的应力响应近似和布局提取算法的算法来解决大布局变化对电路的影响，以获得驱动应力响应的正确几何参数。特别地，这些算法包括来自定向定向的搜索“桶”的特定信息，并且包括用于详细分析半导体器件的特定形状邻域的定向特定的距离测量。算法还适用于使具有单个应力衬垫膜和双应力衬垫（在界面处邻接的两个不同衬垫膜）的器件的建模和应力冲击确定。

103. 发明申请

US20080020531A1 SEMICONDUCTOR DEVICES HAVING TORSIONAL STRESSES 失效
标题翻译：具有扭转应力的半导体器件
公开(公告)号：US20080020531A1
公开(公告)日：2008-01-24
申请号：US11458461
申请日：2006-07-19
申请人： Richard Q. Williams , Dureseti Chidambarrao , John J. Ellis-Monaghan , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik
发明人： Richard Q. Williams , Dureseti Chidambarrao , John J. Ellis-Monaghan , Shreesh Narasimha , Edward J. Nowak , John J. Pekarik
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/7624 , H01L21/823807 , H01L29/66795 , H01L29/7846 , H01L29/7848 , H01L29/785
摘要： A FET structure is provided in which at least one stressor element provided at or near one corner of an active semiconductor region applies a stress in a first direction to one side of a channel region of the FET to apply a torsional stress to the channel region of the FET. In a particular embodiment, a second stressor element is provided at or near an opposite corner of the active semiconductor region to apply a stress in a second direction to an opposite side of a channel region of the FET, the second direction being opposite to the first direction. In this way, the first and second stressor elements cooperate together in applying a torsional stress to the channel region of the FET.
摘要翻译：提供了一种FET结构，其中设置在有源半导体区域的一个角附近或附近的至少一个应激元件将第一方向上的应力施加到FET的沟道区域的一侧，以向该沟道区域的沟道区域施加扭转应力 FET。在特定实施例中，第二应力元件设置在有源半导体区域的相对拐角处或附近，以将第二方向上的应力施加到FET的沟道区域的相对侧，第二方向与第一方向相反方向。以这种方式，第一和第二应激元件协同工作，将扭曲应力施加到FET的沟道区域。

104. 发明申请

US20070296044A1 DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND RELATED METHODS 有权
标题翻译：具有双层蚀刻层和改性硅酸盐层的装置及相关方法
公开(公告)号：US20070296044A1
公开(公告)日：2007-12-27
申请号：US11850968
申请日：2007-09-06
申请人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
发明人： Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha
IPC分类号： H01L29/76
CPC分类号： H01L29/7842 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823864 , H01L29/7843
摘要： The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.
摘要翻译：本发明提供一种具有双重氮化硅衬垫和重整硅化物层的半导体器件以及用于制造这种器件的相关方法。重整的硅化物层具有与未暴露于形成双重氮化硅衬里的硅化物层基本相似的厚度和电阻。本发明的第一方面提供一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到硅化物层，去除第一氮化硅衬垫的一部分，重整硅化物层的一部分在去除步骤期间去除，并且将第二氮化硅衬垫施加到硅化物层。

105. 发明申请

US20070296001A1 MULTIPLE CONDUCTION STATE DEVICES HAVING DIFFERENTLY STRESSED LINERS 失效
标题翻译：具有不同应力衬层的多个导电状态器件
公开(公告)号：US20070296001A1
公开(公告)日：2007-12-27
申请号：US11425511
申请日：2006-06-21
申请人： Dureseti Chidambarrao , David M. Onsongo
发明人： Dureseti Chidambarrao , David M. Onsongo
IPC分类号： H01L29/768
CPC分类号： H01L29/7833 , H01L21/823412 , H01L29/665 , H01L29/7843 , Y10S438/938
摘要： A field effect transistor (“FET”) is provided which includes an active semiconductor region including a channel region, a first source-drain region and a second source-drain region. A major surface of the active semiconductor region is divided into a mutually exclusive first portion and a second portion. A first liner applies a first stress to the first portion of the major surface, and a second liner applies a second stress to the second portion of the major surface. The first and second stresses are each selected from high tensile stress, high compressive stress and neutral stress, with the first stress being different from the second stress. The liners can help to differentiate a first operating current conducted by the first portion of the FET under one operating condition and a second operating current that is conducted by the second portion of the FET under a different operating condition.
摘要翻译：提供了一种场效应晶体管（“FET”），其包括包括沟道区，第一源极 - 漏极区和第二源极 - 漏极区的有源半导体区。有源半导体区域的主表面被分成相互排斥的第一部分和第二部分。第一衬里将第一应力施加到主表面的第一部分，并且第二衬里将第二应力施加到主表面的第二部分。第一和第二应力分别选自高拉伸应力，高压缩应力和中性应力，第一应力与第二应力不同。衬垫可以帮助区分在一个操作条件下由FET的第一部分传导的第一工作电流和在不同工作条件下由FET的第二部分传导的第二工作电流。

106. 发明申请

US20070275532A1 OPTIMIZED DEEP SOURCE/DRAIN JUNCTIONS WITH THIN POLY GATE IN A FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：优化的深度源/漏极结与场效应晶体管中的多晶栅
公开(公告)号：US20070275532A1
公开(公告)日：2007-11-29
申请号：US11420053
申请日：2006-05-24
申请人： Dureseti Chidambarrao , Yaocheng Liu , Kern Rim
发明人： Dureseti Chidambarrao , Yaocheng Liu , Kern Rim
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/2658 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： A semiconductor structure in which the poly depletion and parasitic capacitance problems with poly-Si gate are reduced is provided as well as a method of making the same. The structure includes a thin poly-Si gate and optimized deep source/drain doping. The method changes the sequence of the different implantations steps and makes it possible to fabricate the structure without having dose loss or doping penetration problems. In accordance with the present invention, a sacrificial hard mask capping layer is used to block the high energy implantation and a 3-1 spacer (off-set spacer, first spacer and second spacer) scheme is used to optimize the source/drain doping profile. With this approach, the dose implanted into the thin poly-Si gate can be increased while the deep source/drain implantation can be optimized without worrying about the penetration problem.
摘要翻译：提供了其中减少多晶硅栅极的多晶硅耗尽和寄生电容问题的半导体结构及其制造方法。该结构包括薄多晶硅栅极和优化的深源极/漏极掺杂。该方法改变了不同植入步骤的顺序，并且使得可以制造结构而没有剂量损失或掺杂渗透问题。根据本发明，牺牲硬掩模覆盖层用于阻挡高能量注入，并且使用3-1间隔物（偏置间隔物，第一间隔物和第二间隔物）方案来优化源极/漏极掺杂分布。通过这种方法，可以增加注入薄多晶硅栅极的剂量，同时可以优化深源/漏植入，而不用担心渗透问题。

107. 发明申请

US20070249126A1 A STRUCTURE AND METHOD FOR FABRICATION OF DEEP JUNCTION SILICON-ON-INSULATOR TRANSISTORS 失效
标题翻译：一种用于制造深层结晶硅绝缘体晶体管的结构和方法
公开(公告)号：US20070249126A1
公开(公告)日：2007-10-25
申请号：US11308685
申请日：2006-04-21
申请人： Dureseti Chidambarrao , Brian Greene , John Ellis-Monaghan
发明人： Dureseti Chidambarrao , Brian Greene , John Ellis-Monaghan
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823814
摘要： A structure and method for fabricating a transistor structure is provided. The method comprises the steps of: (a) providing a substrate including a semiconductor-on-insulator (“SOI”) layer separated from a bulk region of the substrate by a buried dielectric layer. (b) first implanting the SOI layer to achieve a predetermined dopant concentration at an interface of the SOI layer to the buried dielectric layer. and (c) second implanting said SOI layer to achieve predetermined dopant concentrations in a polycrystalline semiconductor gate conductor (“poly gate”) and in source and drain regions disposed adjacent to the poly gate, wherein a maximum depth of the first implanting is greater than a maximum depth of the second implanting.
摘要翻译：提供一种用于制造晶体管结构的结构和方法。该方法包括以下步骤：（a）提供包括绝缘体上半导体（“SOI”）层的衬底，该衬底通过掩埋电介质层与衬底的主体区域分离。（b）首先注入SOI层以在SOI层与掩埋介电层的界面处实现预定的掺杂剂浓度。以及（c）第二次注入所述SOI层以在多晶半导体栅极导体（“多晶硅”）中以及在与所述多晶硅栅极相邻设置的源极和漏极区域中实现预定的掺杂剂浓度，其中所述第一注入的最大深度大于第二次植入的最大深度。

108. 发明申请

US20070158753A1 SEMICONDUCTOR DEVICE STRUCTURE HAVING LOW AND HIGH PERFORMANCE DEVICES OF SAME CONDUCTIVE TYPE ON SAME SUBSTRATE 失效
标题翻译：具有相同基板上的相同导电类型的低性能和高性能器件的半导体器件结构
公开(公告)号：US20070158753A1
公开(公告)日：2007-07-12
申请号：US11306716
申请日：2006-01-09
申请人： John C. Arnold , Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Siddhartha Panda , Brian L. Tessier , Richard Wise
发明人： John C. Arnold , Dureseti Chidambarrao , Ying Li , Rajeev Malik , Shreesh Narasimha , Siddhartha Panda , Brian L. Tessier , Richard Wise
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/0922 , H01L29/6656 , H01L29/7842 , H01L29/7843
摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate a first gate with first spacers, a second gate with second spacers, respective source and drain regions of a same conductive type adjacent to the first gate and the second gate, an isolation region disposed intermediate of the first gate and the second gate, silicides on the first gate, the second gate and respective source and drain regions; forming additional spacers on the first spacers to produce an intermediate structure, and then disposing a stress layer over the entire intermediate structure.
摘要翻译：一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成具有第一间隔物的第一栅极，具有第二间隔物的第二栅极，与第一栅极和第二栅极相邻的相同导电类型的相应源极和漏极区域，设置在第一栅极和第二栅极之间的隔离区域栅极，第一栅极上的硅化物，第二栅极和相应的源极和漏极区域; 在第一间隔物上形成附加间隔物以产生中间结构，然后在整个中间结构上设置应力层。

109. 发明申请

US20070122956A1 TRANSISTOR WITH DIELECTRIC STRESSOR ELEMENT FULLY UNDERLYING THE ACTIVE SEMICONDUCTOR REGION 失效
标题翻译：具有完全基于主动半导体区域的电介质压电元件的晶体管
公开(公告)号：US20070122956A1
公开(公告)日：2007-05-31
申请号：US11164632
申请日：2005-11-30
申请人： Dureseti Chidambarrao , Brian Greene , Kern Rim
发明人： Dureseti Chidambarrao , Brian Greene , Kern Rim
IPC分类号： H01L21/8234 , H01L31/00 , H01L21/336
CPC分类号： H01L29/7849 , H01L21/26513 , H01L21/31675 , H01L21/823807 , H01L21/823878 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78654
摘要： A compressive stress is applied to a channel region of a PFET by structure including a discrete dielectric stressor element that fully underlies the bottom surface of an active semiconductor region in which the source, drain and channel region of the PFET is disposed. In particular, the dielectric stressor element includes a region of collapsed oxide which fully contacts the bottom surface of the active semiconductor region such that it has an area coextensive with an area of the bottom surface. Bird's beak oxide regions at edges of the dielectric stressor element apply an upward force at edges of the dielectric stressor element to impart a compressive stress to the channel region of the PFET.
摘要翻译：压缩应力通过结构施加到PFET的沟道区域，其包括完全位于其中设置有PFET的源极，漏极和沟道区域的有源半导体区域的底表面的离散介电应激元件。特别地，介电应力元件包括与活性半导体区域的底表面完全接触的塌陷氧化物区域，使得其具有与底表面的区域共同延伸的区域。电介质应力元件边缘处的鸟喙氧化物区域在介质应力元件的边缘施加向上的力，以向PFET的沟道区域施加压应力。

110. 发明授权

US07224021B2 MOSFET with high angle sidewall gate and contacts for reduced miller capacitance 有权
标题翻译：具有高角度侧壁栅极的MOSFET和用于降低铣刀电容的触点
公开(公告)号：US07224021B2
公开(公告)日：2007-05-29
申请号：US11162424
申请日：2005-09-09
申请人： Dureseti Chidambarrao , Lawrence A. Clevenger , Omer H. Dokumaci , Kaushik A. Kumar , Huilong Zhu
发明人： Dureseti Chidambarrao , Lawrence A. Clevenger , Omer H. Dokumaci , Kaushik A. Kumar , Huilong Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7836 , H01L21/26586 , H01L21/28518 , H01L21/76804 , H01L29/1083 , H01L29/665 , H01L29/6659
摘要： The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.
摘要翻译：本发明涉及一种FET器件，其具有带有倾斜侧壁的导电栅电极。具体来说，FET器件的侧壁从垂直方向偏移大于约0°且不大于约45°的偏移角。以这种方式，这种导电栅电极具有小于其基表面积的顶表面积。优选地，FET器件还包括源极/漏极金属触点，其特征还在于具有倾斜的侧壁，除了源极/漏极金属触点的偏移角度被布置成使得每个金属触点的顶表面积大于其基底表面区。与具有直壁栅电极和金属接触的常规FET器件相比，本发明的FET器件具有显着减小的栅极与漏极金属接触重叠电容，例如小于约0.07毫微微法每微米沟道宽度。

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