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101. 发明申请

US20070117358A1 EPITAXY LAYER AND METHOD OF FORMING THE SAME 有权
标题翻译：外延层及其形成方法
公开(公告)号：US20070117358A1
公开(公告)日：2007-05-24
申请号：US11622490
申请日：2007-01-12
申请人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
发明人： Pang-Yen Tsai , Liang-Gi Yao , Chun-Chieh Lin , Wen-Chin Lee , Shih-Chang Chen
IPC分类号： H01L27/12 , H01L21/20
CPC分类号： C30B25/00 , C30B29/06 , C30B29/52 , Y10S438/933
摘要： A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.
摘要翻译：提供了形成均匀厚度的外延层的方法以改善表面平坦度。首先提供衬底，然后通过外延在衬底上形成Si基层。通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

102. 发明授权

US07202142B2 Method for producing low defect density strained -Si channel MOSFETS 有权
标题翻译：低缺陷密度应变-Si沟道MOSFET的制造方法
公开(公告)号：US07202142B2
公开(公告)日：2007-04-10
申请号：US10838721
申请日：2004-05-03
申请人： Kuen-Chyr Lee , Liang-Gi Yao , Shih-Chang Chen , Mong-Song Liang
发明人： Kuen-Chyr Lee , Liang-Gi Yao , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/20
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L29/665 , H01L29/78
摘要： A silicon strained channel MOSFET device and method for forming the same the method providing improved wafer throughput and low defect density including the steps of providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane, trisilane, dichlorosilane, and silane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane, trisilane, dichlorosilane, and silane.
摘要翻译：一种硅应变通道MOSFET器件及其形成方法，该方法提供提供晶片生产能力和低缺陷密度的方法，包括提供硅衬底的步骤; 使用选自乙硅烷，丙硅烷，二氯硅烷和硅烷的至少一种沉积前体外延生长第一硅层; 使用选自乙硅烷和丙硅烷的至少一种沉积前体外延生长阶梯级SiGe缓冲层并使第一硅层接触; 使用至少一种选自乙硅烷和丙硅烷的沉积前体外延生长SiGe覆盖层并使其与阶级SiGe缓冲层接触; 并且使用至少一种选自乙硅烷，丙硅烷，二氯硅烷和硅烷的沉积前体外延生长第二硅层。

103. 发明申请

US20070032037A1 Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration 有权
标题翻译：使用自组织原子迁移在体半导体衬底中形成SOI样结构的方法
公开(公告)号：US20070032037A1
公开(公告)日：2007-02-08
申请号：US11546768
申请日：2006-10-12
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.
摘要翻译：通过退火将体硅转变成SOI样结构。沟槽形成在大量衬底中以限定器件位置。沟槽的下部在氢气气氛中在低压下退火。这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。相邻的空洞每个居住在中间位置的一半左右。消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

104. 发明申请

US20070010073A1 Method of forming a MOS device having a strained channel region 审中-公开
标题翻译：形成具有应变通道区域的MOS器件的方法
公开(公告)号：US20070010073A1
公开(公告)日：2007-01-11
申请号：US11175563
申请日：2005-07-06
申请人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee , Shih-Chang Chen , Mong Liang
发明人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee , Shih-Chang Chen , Mong Liang
IPC分类号： H01L21/20 , H01L21/4763
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/76828 , H01L21/76829 , H01L21/823412 , H01L21/82345 , H01L21/823807 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device comprising providing a substrate comprising a first device region, implanting a source/drain region in the first device region, forming a strained capping layer on the source/drain region, super annealing and crystallizing the source/drain region, and removing substantially all of the strained capping layer is provided. The method further includes pre-amorphizing the source/drain region before the super annealing. The strained capping layer may further be formed on a pre-amorphized gate electrode, and the gate electrode is super annealed. The strain is generated and preserved after the removal of the strained capping layer.
摘要翻译：一种形成半导体器件的方法，包括提供包括第一器件区域的衬底，在第一器件区域中注入源极/漏极区域，在源极/漏极区域上形成应变封盖层，超退火并使源极/漏极区域结晶并且提供基本上所有的应变封盖层的去除。该方法还包括在超退火之前对源极/漏极区进行非晶化。应变封盖层可以进一步形成在非晶化的栅电极上，并且栅电极被超退火。在去除应变封盖层后产生并保存菌株。

105. 发明申请

US20060228850A1 Pattern loading effect reduction for selective epitaxial growth 审中-公开
标题翻译：用于选择性外延生长的图案加载效应降低
公开(公告)号：US20060228850A1
公开(公告)日：2006-10-12
申请号：US11100053
申请日：2005-04-06
申请人： Pang-Yen Tsai , Chih-Chien Chang , Indira Yang , Tze-Liang Lee , Shih-Chang Chen
发明人： Pang-Yen Tsai , Chih-Chien Chang , Indira Yang , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238 , H01L21/76
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/66628
摘要： A method of reducing the pattern-loading effect for selective epitaxial growth. The method includes the steps of: forming a mask layer over a substrate; forming an isolation region in the substrate isolating an active region and a dummy active region; removing at least a portion of the mask layer in the active region and thus forming a first opening, the substrate being exposed through the first opening; removing at least a portion of the mask layer in the dummy active region and thus forming a second opening, the substrate being exposed through the second opening; and performing selective epitaxial growth simultaneously on the substrate in the first opening and second openings. By introducing the second opening wherein epitaxial growth occurs, the pattern density is more uniform and thus the pattern-loading effect is reduced.
摘要翻译：降低选择性外延生长的图案负载效应的方法。该方法包括以下步骤：在衬底上形成掩模层; 在所述衬底中形成隔离有源区和虚拟有源区的隔离区; 去除所述有源区域中的所述掩模层的至少一部分，从而形成第一开口，所述基板通过所述第一开口露出; 去除所述虚拟有源区域中的所述掩模层的至少一部分，从而形成第二开口，所述基板通过所述第二开口露出; 以及在所述第一开口和所述第二开口中的所述衬底上同时执行选择性外延生长。通过引入其中发生外延生长的第二开口，图案密度更均匀，因此图案加载效应降低。

106. 发明申请

US20060154425A1 Semiconductor device and method for fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060154425A1
公开(公告)日：2006-07-13
申请号：US11032439
申请日：2005-01-10
申请人： Ming-Ho Yang , Karen Mai , Liang-Gi Yao , Shih-Chang Chen
发明人： Ming-Ho Yang , Karen Mai , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/517 , H01L21/28061 , H01L21/28194 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device and method for fabricating the same. The semiconductor device comprises a substrate with a gate stack thereon, wherein the gate stack comprises a high-k dielectric layer and a conductive layer sequentially overlying a portion of the substrate. An oxidation-proof layer overlies sidewalls of the gate stack. A pair of insulating spacers oppositely overlies sidewalls of the gate stack and the oxidation-proof layers thereon and a pair of source/drain regions is oppositely formed in the substrate adjacent to the gate stack, wherein the oxidation-proof layer suppresses oxidation encroachment between the gate stack and the substrate.
摘要翻译：一种半导体器件及其制造方法。半导体器件包括其上具有栅极堆叠的衬底，其中栅极堆叠包括高k电介质层和顺序地覆盖衬底的一部分的导电层。防氧化层覆盖在栅叠层的侧壁上。一对绝缘隔片相对地覆盖在栅堆叠的侧壁和其上的防氧化层上，并且一对源极/漏极区域相邻地形成在与栅极叠层相邻的衬底中，其中防氧化层抑制了栅极叠层之间的氧化侵蚀栅极堆叠和衬底。

107. 发明申请

US20060094194A1 Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology 审中-公开
标题翻译：用于低于90NM CMOS技术的低温高应力氮化膜的高级一次性间隔工艺
公开(公告)号：US20060094194A1
公开(公告)日：2006-05-04
申请号：US10982115
申请日：2004-11-04
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device comprises providing a gate electrode having exposed side walls formed in a substrate, forming dummy spacers on the gate electrode exposed side walls, performing a first implant to form source and drain implants, forming a capping layer over the gate electrode, the dummy sidewall spacers, and the source and drain, performing a first anneal, and removing the capping layer and the dummy sidewall spacers.
摘要翻译：一种形成半导体器件的方法包括提供栅电极，其具有形成在衬底中的暴露的侧壁，在栅极电极暴露的侧壁上形成虚设间隔物，执行第一注入以形成源极和漏极注入，在栅极上形成覆盖层电极，虚拟侧壁间隔物以及源极和漏极，执行第一退火，以及去除覆盖层和虚设侧壁间隔物。

108. 发明申请

US20060094192A1 Method for treating base oxide to improve high-K material deposition 审中-公开
标题翻译：用于处理基底氧化物以改善高K材料沉积的方法
公开(公告)号：US20060094192A1
公开(公告)日：2006-05-04
申请号：US11048487
申请日：2005-01-31
申请人： Ming-Ho Yang , Liang-Gei Yao , Shih-Chang Chen
发明人： Ming-Ho Yang , Liang-Gei Yao , Shih-Chang Chen
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L21/02307 , C23C16/0227 , H01L21/0206 , H01L21/02181 , H01L21/022 , H01L21/02271 , H01L21/0228 , H01L21/02312 , H01L21/02315 , H01L21/28185 , H01L21/28194 , H01L21/3141 , H01L21/3144 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A method for forming a high-K material layer in a semiconductor device fabrication process including providing a silicon semiconductor substrate or thermally growing interfacial oxide layer comprising silicon dioxide over the silicon substrate; treating with an aqueous base solution or nitridation and depositing a high-K material layer.
摘要翻译：一种在半导体器件制造工艺中形成高K材料层的方法，包括在硅衬底上提供包含二氧化硅的硅半导体衬底或热生长界面氧化物层; 用碱水溶液处理或氮化处理，沉积高K材料层。

109. 发明授权

US07034506B2 Emergency lighting equipment with automatic charge/discharge and monitoring system 失效
标题翻译：应急照明设备具有自动充放电监控系统
公开(公告)号：US07034506B2
公开(公告)日：2006-04-25
申请号：US10707739
申请日：2004-01-08
申请人： Shih-Chang Chen , Tsair Rong Chen
发明人： Shih-Chang Chen , Tsair Rong Chen
IPC分类号： H02J7/00
CPC分类号： H02J7/0029 , H02J7/0047 , H02J7/045 , H02J9/065
摘要： An emergency lighting equipment with an automatic charge/discharge and monitoring system is provided. The emergency lighting equipment comprises an operating mode control circuit, a rectify/voltage-divide and voltage regulation circuit, a main control unit, an illuminating apparatus and a battery. A battery discharge operating is initiated when the main control unit detects the passage of a preset period without any battery discharge operation. The main control unit also terminates a battery discharging operation when the discharge operation is completed and terminates a battery charging operation after the battery has been float-charged for a preset period of time. The emergency lighting equipment may include a battery state inspection circuit for issuing a warning signal when the battery is found to be defective.
摘要翻译：提供具有自动充放电监控系统的应急照明设备。应急照明设备包括操作模式控制电路，整流/分压和调压电路，主控单元，照明装置和电池。当主控制单元在没有任何电池放电操作的情况下检测到预设时段的通过时，开始电池放电操作。主控制单元还在放电操作完成时终止电池放电操作，并且在电池已充电一段预定时间后终止电池充电操作。应急照明设备可以包括电池状态检查电路，用于当发现电池有缺陷时发出警告信号。

110. 发明申请

US20060035477A1 Methods and systems for rapid thermal processing 审中-公开
标题翻译：快速热处理的方法和系统
公开(公告)号：US20060035477A1
公开(公告)日：2006-02-16
申请号：US10916495
申请日：2004-08-12
申请人： Karen Mai , Ming-Ho Yang , Tze Lee , Shih-Chang Chen , Chun-Feng Nieh
发明人： Karen Mai , Ming-Ho Yang , Tze Lee , Shih-Chang Chen , Chun-Feng Nieh
IPC分类号： H01L21/477 , F27D11/00
CPC分类号： F27D99/0006 , F27B17/0025 , F27D5/0037 , F27D2099/0026 , H01L21/67115 , H01L21/67248
摘要： Methods for rapid thermal processing of semiconductor substrates are provided. An exemplary method comprises directing radiant heat energy emitted from a heat source toward a backside surface of the semiconductor substrate. Systems for rapid thermal processing also are provided.
摘要翻译：提供了半导体衬底的快速热处理方法。一种示例性的方法包括将从热源发射的辐射热能引导到半导体衬底的背面。还提供用于快速热处理的系统。

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