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101. 发明授权

US06680875B2 Semiconductor device, such as a synchronous DRAM, including a control circuit for reducing power consumption 有权
标题翻译：诸如同步DRAM的半导体器件，包括用于降低功耗的控制电路
公开(公告)号：US06680875B2
公开(公告)日：2004-01-20
申请号：US10259579
申请日：2002-09-30
申请人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
IPC分类号： G11C800
CPC分类号： G11C5/063 , G11C5/14 , G11C5/147 , G11C7/1072 , G11C8/12 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A semiconductor device comprising a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits is deactivated.
摘要翻译：一种半导体器件，包括多个存储体和对应于存储体的多个电源电路。每个存储体被激活命令独立地激活。给定外部提供的电压，每个电源电路输出预定的内部电源电压。每个电源电路的输出连接到相应的存储体。响应于用于激活存储体之一的命令，相应的电源电路被激活，而剩余的电源电路被去激活。

102. 发明授权

US06643923B1 Processes for manufacturing flexible wiring boards 失效
标题翻译：制造柔性布线板的工艺
公开(公告)号：US06643923B1
公开(公告)日：2003-11-11
申请号：US09744572
申请日：2001-02-28
申请人： Hiroyuki Hishinuma , Hideyuki Kurita , Ryo Ito , Masayuki Nakamura
发明人： Hiroyuki Hishinuma , Hideyuki Kurita , Ryo Ito , Masayuki Nakamura
IPC分类号： H05K302
CPC分类号： H05K3/4007 , H01L21/4853 , H01L21/4857 , H01L23/4985 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H05K3/423 , H05K3/4647 , H05K2201/0154 , H05K2201/0195 , H05K2201/0347 , H05K2201/0355 , H05K2201/0367 , H05K2201/09481 , H05K2201/09563 , H05K2203/0759 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49147 , Y10T29/49155 , H01L2224/05624 , H01L2924/00014
摘要： A process for manufacturing a flexible wiring board according to the present invention includes growing metal bumps (16) using a mask film patterned by photolithography. Fine openings are formed in a polyimide film with good precision allowing fine metal bumps (16) to be formed with good precision. After metal bumps (16) have been formed, the mask film is removed and a liquid resin material is applied and dried to form a coating, which is then cured into a resin film. The coating can be etched at surface portions during coating stage to expose the tops of metal bumps (16).
摘要翻译：根据本发明的柔性线路板的制造方法包括使用通过光刻图案化的掩模膜生长金属凸块（16）。在聚酰亚胺膜中形成精细的开口，精度高，能够精确地形成精细的金属凸块（16）。在形成金属凸块（16）之后，除去掩模膜并施加液体树脂材料并干燥以形成涂层，然后将其固化成树脂膜。涂层可以在涂覆阶段在表面部分进行蚀刻以暴露金属凸块（16）的顶部。

103. 发明授权

US06583364B1 Ultrasonic manufacturing apparatuses, multilayer flexible wiring boards and processes for manufacturing multilayer flexible wiring boards 有权
标题翻译：超声波制造装置，多层柔性布线板以及多层挠性布线板的制造方法
公开(公告)号：US06583364B1
公开(公告)日：2003-06-24
申请号：US09642638
申请日：2000-08-22
申请人： Hideyuki Kurita , Masanao Watanabe , Masayuki Nakamura , Mitsuhiro Fukuda , Hiroyuki Usui
发明人： Hideyuki Kurita , Masanao Watanabe , Masayuki Nakamura , Mitsuhiro Fukuda , Hiroyuki Usui
IPC分类号： H05K100
CPC分类号： H05K3/4635 , H01L2224/1147 , H01L2924/01019 , H05K1/0393 , H05K3/005 , H05K3/28 , H05K3/423 , H05K3/4617 , H05K3/4647 , H05K3/4652 , H05K2201/0195 , H05K2201/0355 , H05K2201/09563 , H05K2203/0195 , H05K2203/0285 , H05K2203/1189 , Y10T29/49124 , Y10T29/49126 , Y10T29/49155
摘要： The present invention pertains to a multilayer flexible wiring board. The multilayer flexible wiring board including first and second patterned wiring layers, a resin film interposed between a surface of the first wiring layer and a surface of the second wiring layer, and a bump connected to the surface of the second wiring layer, wherein the resin film is adapted to form an opening when the bump to force into the resin film and an ultrasonic wave is applied to the bump and the bump is left in the opening to electrically connect the top of the bump to the first wiring layer.
摘要翻译：本发明涉及一种多层柔性布线板。多层挠性布线板包括第一和第二图案化布线层，介于第一布线层的表面和第二布线层的表面之间的树脂膜和连接到所述第二布线层的表面，其中当所述凸起压入所述树脂膜中时，所述树脂膜适于形成开口，并且超声波被施加到所述凸起，并且所述凸块被留在所述开口中以电连接所述第二布线层的顶部碰到第一个接线层。

104. 发明授权

US6057290A Angiogenesis inhibitor 失效
标题翻译：血管生成抑制剂
公开(公告)号：US6057290A
公开(公告)日：2000-05-02
申请号：US740069
申请日：1996-10-24
申请人： Chiho Fukiage , Mitsuyoshi Azuma , Jun Inoue , Masayuki Nakamura , Yuka Yoshida
发明人： Chiho Fukiage , Mitsuyoshi Azuma , Jun Inoue , Masayuki Nakamura , Yuka Yoshida
IPC分类号： A61K38/55 , C07C311/19 , C07D303/48 , A61K38/00 , C07K5/00 , C07K7/00
CPC分类号： A61K38/55 , C07C311/19 , C07D303/48
摘要： An angiogenesis inhibitor comprising a cysteine protease inhibitory compound. As the preferable cysteine protease inhibitory compound, epoxysuccinic acid compounds, peptide halohydrazide compounds, calpain inhibitory compounds, compounds of the formula (I) ##STR1## and compounds of the formula (VI) ##STR2## can be used. The angiogenesis inhibitor of the present invention suppresses new formation of blood vessels in the living tissues, so that it can be used as a superior therapeutic or prophylactic agent of angiogenesis associated with wound healing, inflammation, growth of tumor and the like; and angiogenesis as seen in diabetic retinopathy, prematurity retinopathy, retinal venous occlusion, senile discoid macular degeneration and the like, as well as for prevention of metastasis of tumors.
摘要翻译：一种包含半胱氨酸蛋白酶抑制化合物的血管生成抑制剂。作为优选的半胱氨酸蛋白酶抑制化合物，可以使用环氧琥珀酸化合物，肽卤代酰肼化合物，钙蛋白酶抑制化合物，式（I）的化合物和式（VI）的化合物。本发明的血管发生抑制剂抑制活组织中血管的新形成，可以用作与伤口愈合，炎症，肿瘤生长等有关的血管生成的优异治疗或预防剂。和血管生成，如糖尿病视网膜病变，早产儿视网膜病变，视网膜静脉闭塞，老年性盘状黄斑变性等，以及用于预防肿瘤转移。

105. 发明授权

US5966341A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5966341A
公开(公告)日：1999-10-12
申请号：US982398
申请日：1997-12-02
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C11/4097 , H01L21/8242 , H01L27/105 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10805 , G11C11/408 , G11C11/4096 , G11C11/4097 , G11C7/10 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

106. 发明授权

US5953278A Data sequencing and registering in a four bit pre-fetch SDRAM 失效
标题翻译：数据排序和注册在四位预取SDRAM
公开(公告)号：US5953278A
公开(公告)日：1999-09-14
申请号：US891596
申请日：1997-07-11
申请人： Hugh P. McAdams , Paulette Thurston , Masayuki Nakamura
发明人： Hugh P. McAdams , Paulette Thurston , Masayuki Nakamura
IPC分类号： G11C7/10 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1042 , G11C11/4096 , G11C7/1018 , G11C7/1048 , G11C7/1072
摘要： A memory device uses data circuitry to connect data lines extending from memory cell arrays to data signal bond pads. The data circuitry connect four data lines to one data signal bond pad. The data circuitry include data sequencer circuits, parallel data in circuits and serial data register circuits. The parallel data in circuits operate to write data to the memory device. The serial data register circuits operate to read and write data. The data sequencer circuits operate to connect the data lines to the bond pad in a selected order in a four bit pre-fetch architecture for normal and interleaved data modes.
摘要翻译：存储器件使用数据电路将从存储单元阵列延伸的数据线连接到数据信号焊盘。数据电路将四条数据线连接到一个数据信号焊盘。数据电路包括数据定序器电路，电路中的并行数据和串行数据寄存器电路。电路中的并行数据用于将数据写入存储器件。串行数据寄存器电路用于读取和写入数据。数据定序器电路用于以正常和交织的数据模式的四位预取架构中的所选顺序将数据线连接到接合焊盘。

107. 发明授权

US5905685A Dynamic memory 失效
标题翻译：动态内存
公开(公告)号：US5905685A
公开(公告)日：1999-05-18
申请号：US951734
申请日：1997-10-15
申请人： Masayuki Nakamura , Masatoshi Hasegawa , Seiji Narui , Yousuke Tanaka , Shinichi Miyatake , Shuichi Kubouchi , Kazuhiko Kajigaya
发明人： Masayuki Nakamura , Masatoshi Hasegawa , Seiji Narui , Yousuke Tanaka , Shinichi Miyatake , Shuichi Kubouchi , Kazuhiko Kajigaya
IPC分类号： G11C11/407 , G11C11/401 , G11C11/4074 , G11C11/408 , G11C11/409 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C11/4074 , G11C11/408 , G11C11/4087
摘要： In a dynamic RAM having a memory cell array in which a dynamic memory cell is arranged at an intersection between a word line and one of a pair of bit lines, a select level signal corresponding to a supply voltage and an unselect level signal corresponding to a negative potential lower than circuit ground potential are supplied to the word line. A signal of a memory cell read to the pair of bit lines by a sense amplifier that operates on the circuit ground potential and an internal voltage formed by dropping the supply voltage by an amount equivalent to the threshold voltage of the address select MOSFET is amplified. The dynamic RAM has an oscillator that receives the supply voltage and circuit ground potential and a circuit that receives an oscillation pulse generated by the oscillator to generate the negative potential.
摘要翻译：在具有存储单元阵列的动态RAM中，其中动态存储单元布置在字线和一对位线中的一个位线之间的交叉点处，对应于电源电压的选择电平信号和对应于低于电路接地电位的负电位被提供给字线。通过由电路接地电位进行工作的读出放大器对一对位线读取的存储单元的信号和通过将电源电压降低等于地址选择MOSFET的阈值电压的量而形成的内部电压被放大。动态RAM具有接收电源电压和电路接地电位的振荡器，以及接收由振荡器产生的振荡脉冲以产生负电位的电路。

108. 发明授权

US5835445A Semiconductor integrated circuit device having a synchronous output function with a plurality of external clocks 失效
标题翻译：具有同步输出功能的多个外部时钟的半导体集成电路器件
公开(公告)号：US5835445A
公开(公告)日：1998-11-10
申请号：US714465
申请日：1996-09-16
申请人： Masayuki Nakamura
发明人： Masayuki Nakamura
IPC分类号： G11C11/407 , G11C5/06 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C11/34 , G11C11/401 , G11C29/00
CPC分类号： G11C7/1072 , G11C29/80 , G11C29/84 , G11C7/22
摘要： The present invention is a method and apparatus for reducing the effects of transmission line impedance on the clock signal in a semiconductor device. In a departure from the prior art, the present invention includes multiple clock inputs, located near the device's synchronous input/output ports, reducing the maximum distance that any single internal clock signal must travel and thereby reducing the amount of delay caused by the effects of transmission line impedance on the internal clock signals. The present invention also includes a read only memory ("ROM") to improve the speed of the device and to provide additional space in the highly congested areas between the column decoder and address ports of the device. The ROM is programmed to decipher row address for information that would be beneficial in a redundant column access.
摘要翻译：本发明是一种降低半导体器件中传输线阻抗对时钟信号的影响的方法和装置。与现有技术不同，本发明包括位于设备同步输入/输出端口附近的多个时钟输入，减少了任何单个内部时钟信号必须行进的最大距离，从而减少了由于传输线阻抗对内部时钟信号的影响。本发明还包括一个只读存储器（“ROM”），用于提高设备的速度并且在列解码器和设备的地址端口之间的高度拥塞的区域中提供额外的空间。 ROM被编程为解密行地址以获得在冗余列访问中有益的信息。

109. 发明授权

US5796187A Electric actuator 失效
标题翻译：电动执行器
公开(公告)号：US5796187A
公开(公告)日：1998-08-18
申请号：US855448
申请日：1997-05-13
申请人： Shigekazu Nagai , Shuuzou Sakurai , Masayuki Nakamura
发明人： Shigekazu Nagai , Shuuzou Sakurai , Masayuki Nakamura
IPC分类号： H02K7/06 , B23Q5/40 , B23Q11/08 , F16H25/20
CPC分类号： B23Q5/40 , B23Q11/08 , F16H25/20 , F16H2025/2075
摘要： Disclosed is an electric actuator which makes it possible to prevent a driving force-transmitting shaft from adhesion of dust or the like, and eliminate any fear for deterioration of driving force-transmitting function. A hole is defined in a body which is arranged to extend in a vertical direction. A motor is secured to one end of the body. A feed screw is coaxially connected to a rotary shaft of the motor. The feed screw is rotatably supported by angular contact ball bearings. A feed nut is engaged with the feed screw. The hole is slidably engaged with a cylinder member which is formed to be cylindrical and lengthy. The cylinder member surrounds the feed screw. The feed nut is secured to one end of the cylinder member, and a bracket is secured to the other end thereof.
摘要翻译：公开了一种电致动器，其能够防止驱动力传递轴粘附灰尘等，并且消除对驱动力传递功能的劣化的任何恐惧。在主体中限定了一个孔，该主体被布置为在垂直方向上延伸。马达固定在身体的一端。进给螺杆与电机的旋转轴同轴连接。进给螺杆由角接触球轴承可转动地支承。进给螺母与进给螺杆啮合。该孔与形成为圆柱形和冗长的圆筒构件可滑动地接合。气缸构件围绕进给螺杆。进给螺母固定在缸体的一端，支架固定在其另一端。

110. 发明授权

US5276648A Testing method for a semiconductor memory device 失效
标题翻译：半导体存储器件的测试方法
公开(公告)号：US5276648A
公开(公告)日：1994-01-04
申请号：US818274
申请日：1992-01-08
申请人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
发明人： Kazumasa Yanagisawa , Tatsuyuki Ohta , Tetsu Udagawa , Kyoko Ishii , Hitoshi Miwa , Atsushi Nozoe , Masayuki Nakamura , Tetsurou Matsumoto , Yoshitaka Kinoshita , Yoshiaki Ouchi , Hiromi Tsukada , Shoji Wada , Kazuo Mihashi , Yutaka Kobayashi , Goro Kitsukawa
IPC分类号： G11C11/409 , G05F3/24 , G11C11/401 , G11C11/403 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/10 , H01L27/108 , G11C13/00
CPC分类号： G11C29/80 , G11C11/4085 , G11C29/28 , G11C29/34 , G11C29/46 , G11C29/50 , G11C11/401
摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.
摘要翻译：提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

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