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91. 发明授权

US08749271B2 Methods for synchronizing high-speed signals in a digital phase detector 有权
标题翻译：用于在数字相位检测器中同步高速信号的方法
公开(公告)号：US08749271B2
公开(公告)日：2014-06-10
申请号：US11498365
申请日：2006-08-03
申请人： Feng Lin
发明人： Feng Lin
IPC分类号： G01R25/00
CPC分类号： H03D13/004
摘要： Methods of synchronizing signals are provided. Specifically, a detector is provided in the digital phase detector to detect certain failure conditions that may result from clock skew and duty cycle distortion. If the condition is detected, an adjusted signal is generated and the adjusted signal is synchronized with the reference signal. By using the generated signal to provide a lock if certain conditions arise, adjustment errors resulting from duty cycle distortion and clock skew can be minimized.
摘要翻译：提供同步信号的方法。具体地，在数字相位检测器中提供检测器以检测可能由时钟偏移和占空比失真引起的某些故障状况。如果检测到条件，则生成调整后的信号，调整后的信号与参考信号同步。通过使用产生的信号来提供锁定，如果出现某些情况，可以将由占空比失真和时钟偏移引起的调整误差降到最小。

92. 发明授权

US08564347B2 Phase detector circuit for automatically detecting 270 and 540 degree phase shifts 有权
标题翻译：用于自动检测270度和540度相移的相位检测器电路
公开(公告)号：US08564347B2
公开(公告)日：2013-10-22
申请号：US13607045
申请日：2012-09-07
申请人： Min Xu , Ming-Ju E. Lee
发明人： Min Xu , Ming-Ju E. Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03D13/004 , H03L7/089 , H03L7/0891
摘要： Embodiments include implementing a phase detector for a delay-locked loop (DLL) circuit that is operable to detect substantially 270 degree and substantially 540 degree phase differences between two clock signals. In an embodiment, a DLL circuit comprises a delay line receiving a system clock signal and generating phase shifted clock signals, a phase detector receiving the system clock signal and phase shifted clock signal, and configured to generate corresponding up and down signals upon detection of a phase shift of substantially 270 degrees between the system clock signal and the phase shifted clock signal, a charge pump coupled to the phase detector, and configured to receive the up and down signals and generate a control signal responsive to thereto, and a regulator circuit to receive the control signal from the charge pump and generate a voltage control signal to the delay chain to control delay of the system clock signal.
摘要翻译：实施例包括实现用于延迟锁定环路（DLL）电路的相位检测器，该电路可操作以检测两个时钟信号之间基本上270度和基本上540度的相位差。在一个实施例中，DLL电路包括接收系统时钟信号并产生相移时钟信号的延迟线，接收系统时钟信号和相移时钟信号的相位检测器，并且被配置为在检测到在系统时钟信号和相移时钟信号之间基本为270度的相移，耦合到相位检测器的电荷泵，并且被配置为接收上升和下拉信号并响应于此产生控制信号，以及调节器电路从电荷泵接收控制信号，并产生到延迟链的电压控制信号，以控制系统时钟信号的延迟。

93. 发明授权

US08315349B2 Bang-bang phase detector with sub-rate clock 有权
标题翻译： Bang-bang相位检测器带子速率时钟
公开(公告)号：US08315349B2
公开(公告)日：2012-11-20
申请号：US12258440
申请日：2008-10-26
申请人： Riccardo Badalone
发明人： Riccardo Badalone
IPC分类号： H03D3/24
CPC分类号： H03D13/004
摘要： The present invention describes methods and circuitry for a sub-rate bang-bang phase detector, in which the reference clock has frequency that is a fraction of the bit rate of the received data stream. The sub-rate bang-bang phase detector is enabled by multiple phases of the reference clock.
摘要翻译：本发明描述了用于子速率爆炸相位检测器的方法和电路，其中参考时钟的频率是接收数据流的比特率的一部分。子速率爆炸相位检测器由参考时钟的多个相位启用。

94. 发明申请

US20120200325A1 LOW JITTER CLOCK RECOVERY CIRCUIT 审中-公开
标题翻译：低抖动时钟恢复电路
公开(公告)号：US20120200325A1
公开(公告)日：2012-08-09
申请号：US13312773
申请日：2011-12-06
申请人： Carl William Werner
发明人： Carl William Werner
IPC分类号： H03L7/06
CPC分类号： H04L7/0331 , H03D13/004 , H03L7/07 , H03L7/081 , H03L7/087 , H03L7/0891 , H03L7/091 , H04L7/033
摘要： A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.
摘要翻译：时钟恢复电路包括用于测量来自压控振荡器（VCO）的第一时钟信号与数据信号之间的相位差的第一相位检测器。基于该相位差响应于控制信号的移相器调整输入时钟信号的相位以产生第二时钟信号。测量第一时钟信号和第二时钟信号之间的相位差，并将所得到的信号进行低通滤波，以得到用于控制VCO的控制信号。包括VCO的锁相环滤除抖动。

95. 发明授权

US08107580B2 Method and apparatus for generating a phase dependent control signal 有权
标题翻译：用于产生相位相关控制信号的方法和装置
公开(公告)号：US08107580B2
公开(公告)日：2012-01-31
申请号：US12562709
申请日：2009-09-18
申请人： Ronnie M. Harrison
发明人： Ronnie M. Harrison
IPC分类号： H03D3/24 , H03L7/06
CPC分类号： G11C7/1072 , G11C7/222 , H03D13/004 , H03K5/131 , H03K5/133 , H03K5/135 , H03L7/07 , H03L7/0812 , H03L7/085 , H03L7/087 , H03L7/0896
摘要： A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating select signals having duty cycles corresponding to the phase relationship between the clock edges of the first and second clock signals. The phase detector also includes a charge pump that receives select signals from the phase detector circuits and produces an increasing or decreasing control signal when the first and second clock signals do not have the predetermined phase relationship, and a non-varying control signal when the first and second clock signals do have the predetermined phase relationship. The control signal may be used to adjust the delay value of a voltage-controlled delay circuit in order to adjust the phase relationship between the first and second clock signals to have a predetermined phase relationship.
摘要翻译：相位检测器根据第一和第二时钟信号之间的相位关系产生相位相关的控制信号。相位检测器包括接收第一和第二时钟信号的第一和第二相位检测器电路，并产生具有对应于第一和第二时钟信号的时钟沿之间的相位关系的占空比的选择信号。相位检测器还包括电荷泵，其在相位检测器电路接收选择信号，并且当第一和第二时钟信号不具有预定的相位关系时产生增加或减小的控制信号，当第一和第二时钟信号不具有预定的相位关系时，并且第二时钟信号具有预定的相位关系。控制信号可以用于调整压控延迟电路的延迟值，以便调整第一和第二时钟信号之间的相位关系以具有预定的相位关系。

96. 发明授权

US08073093B2 Phase synchronous device and method for generating phase synchronous signal 有权
标题翻译：相位同步装置及相位同步信号生成方法
公开(公告)号：US08073093B2
公开(公告)日：2011-12-06
申请号：US11776148
申请日：2007-07-11
申请人： Ki Won Lee
发明人： Ki Won Lee
IPC分类号： H03D3/24
CPC分类号： H03D13/004 , H03L7/0812 , H03L7/083 , H03L7/0895 , H03L7/095
摘要： Disclosed are a phase synchronous device for improving jitter of an output signal and a method for generating a phase synchronous signal. The phase synchronous device includes a phase detector detecting a phase difference between first and second signals to output a phase detection signal and a locking signal; a control signal generator adjusting a slope of the phase detection signal in response to the locking signal; and a charge pumping unit outputting a control voltage in response to an output of the control signal generator. The speed of a control signal applied to the charge pumping unit is adjusted in response to the locking signal, so that a peak current is reduced, and thus jitter of an output signal is improved by being reduced or minimized.
摘要翻译：公开了一种用于改善输出信号的抖动的相位同步装置和用于产生相位同步信号的方法。相位同步装置包括相位检测器，检测第一和第二信号之间的相位差，以输出相位检测信号和锁定信号; 控制信号发生器，响应于锁定信号调节相位检测信号的斜率; 以及电荷泵送单元，其响应于所述控制信号发生器的输出而输出控制电压。响应于锁定信号调整施加到电荷泵送单元的控制信号的速度，从而降低峰值电流，从而通过减小或最小化来提高输出信号的抖动。

97. 发明授权

US07880520B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07880520B2
公开(公告)日：2011-02-01
申请号：US12341296
申请日：2008-12-22
申请人： Masaya Sumita
发明人： Masaya Sumita
IPC分类号： H03L7/00
CPC分类号： G11C7/227 , G06F1/10 , G06F1/24 , G11C7/1072 , G11C7/222 , G11C2207/2281 , H03D13/004 , H03L7/07 , H03L7/0814 , H03L7/0891 , H03L7/0895 , H03L7/0898 , H03L7/18
摘要： During a period of preparation for actual operation, a reference clock is supplied to both a comparison clock input portion and a feedback clock input portion of a phase comparator while a feedback loop of a PLL (phase-locked loop) is interrupted, and a delay of a reset signal within the phase comparator is adjusted so as to reduce a detection dead zone of phase differences in the phase comparator.
摘要翻译：在实际操作准备期间，当PLL（锁相环）的反馈环路被中断时，将参考时钟提供给相位比较器的比较时钟输入部分和反馈时钟输入部分，并且延迟调整相位比较器内的复位信号，以减少相位比较器中相位差的检测死区。

98. 发明授权

US07873130B2 Frequency comparator utilizing enveloping-event detection via symbolic dynamics of fixed or modulated waveforms 有权
标题翻译：频率比较器通过固定或调制波形的符号动力学进行包络事件检测
公开(公告)号：US07873130B2
公开(公告)日：2011-01-18
申请号：US11463557
申请日：2006-08-09
申请人： Lester F. Ludwig
发明人： Lester F. Ludwig
IPC分类号： H03D3/24 , H03D13/00
CPC分类号： H03D13/004
摘要： Systems, algorithms, circuits, and methods for pattern detection of signature events in signal dynamics defined by instantaneous states of applied square-wave signals. Selected patterns may be recognized individually or in equivalence classes, and detection may be implemented via state or transition analysis. Varieties of conditions may be detected in parallel, including phase, ambiguity states, and frequency comparison. One embodiment realizes a real-time frequency comparator for asynchronous square-wave signals. Realizations detect various classes of symmetry conditions unique to enveloping events occurring for these classes of square-wave signal pairs. This approach provides feedback-free implementations operating over an extremely wide frequency range and does not require signals of quadrature form. A typical logic circuit implementation involves two to four flip-flops, or two-stage two-bit shift registers, and modest combinational logic. The resulting system can be readily implemented as a utility integrated circuit of modest scale or as a small-scale “IP core” within larger system-on-a-chip (SoIC) devices.
摘要翻译：用于由施加的方波信号的瞬时状态定义的信号动态中的签名事件的模式检测的系统，算法，电路和方法。所选择的模式可以被单独或等价类别识别，并且可以通过状态或转换分析实现检测。可以并行检测各种条件，包括相位，模糊状态和频率比较。一个实施例实现了用于异步方波信号的实时频率比较器。实现检测对于这些类型的方波信号对发生的包围事件唯一的各种对称条件。这种方法提供了在非常宽的频率范围内工作的无反馈实现，并且不需要正交形式的信号。典型的逻辑电路实现涉及两到四个触发器或两级两位移位寄存器和适度的组合逻辑。所产生的系统可以容易地实现为较大规模的公用事业集成电路或作为较小的片上系统（SoIC）设备中的小规模“IP核”。

99. 发明授权

US07826583B2 Clock data recovery apparatus 有权
标题翻译：时钟数据恢复装置
公开(公告)号：US07826583B2
公开(公告)日：2010-11-02
申请号：US11819807
申请日：2007-06-29
申请人： Chun-Seok Jeong , Jae-Jin Lee , Chang-Sik Yoo , Jung-June Park , Young-Suk Seo
发明人： Chun-Seok Jeong , Jae-Jin Lee , Chang-Sik Yoo , Jung-June Park , Young-Suk Seo
IPC分类号： H03D3/24 , H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03D13/004
摘要： A clock data recovery apparatus includes a phase looked loop unit, a voltage control delay line, a phase detection unit, a charge pump unit, and a loop filter unit. The phase looked loop unit outputs a plurality of clock signals which are different from each other in phase and of which frequency is lower than that of data. The voltage control delay line outputs recovered clock signals by delaying the clock signals according to input voltage levels. The phase detection unit outputs recovered data in synchronization with the clock signals, respectively and outputs increment and decrement signals which have wider pulse width than the data by comparing the recovered clock signals with the data. The charge pump unit outputs a corresponding current in response to the increment and decrement signals. The loop filter unit determines an amount of delay in the voltage control delay line by outputting the voltage.
摘要翻译：时钟数据恢复装置包括相位循环单元，电压控制延迟线，相位检测单元，电荷泵单元和环路滤波器单元。相位循环单元输出相位不同的多个时钟信号，其频率低于数据的时钟信号。电压控制延迟线通过根据输入电压电平延迟时钟信号来输出恢复的时钟信号。相位检测单元分别与时钟信号同步地输出恢复的数据，并通过将恢复的时钟信号与数据进行比较，输出比数据宽的脉冲宽度的增减信号。电荷泵单元响应于增量和减量信号输出相应的电流。环路滤波器单元通过输出电压来确定电压控制延迟线中的延迟量。

100. 发明授权

US07792497B2 Method and apparatus for frequency synthesizing 有权
标题翻译：频率合成方法和装置
公开(公告)号：US07792497B2
公开(公告)日：2010-09-07
申请号：US11862290
申请日：2007-09-27
申请人： Wei-Zen Chen , Tai-You Lu
发明人： Wei-Zen Chen , Tai-You Lu
IPC分类号： H04B1/40
CPC分类号： H03D13/004 , H03L7/193
摘要： A method and an apparatus for frequency synthesizing are provided for a wireless communication system. In a frequency synthesizer, a phase lock loop (PLL) circuit generates a first elemental frequency based on a reference frequency and a unity frequency. A first division module then divides the first elemental frequency to generate a second elemental frequency. A second division module divides the second elemental frequency a multiple of times to generate the unity frequency and a plurality of intermediate frequencies each having an exponential ratio to the unity frequency by a power of two. A second mixer is provided to mix one of the intermediate frequencies with the unity frequency to generate a step frequency, and a first mixer mixes the step frequency with one of the first and second elemental frequencies to generate an output frequency having a variety covering all frequency bands in an Ultra-Wide-Band (UWB) spectrum.
摘要翻译：为无线通信系统提供频率合成的方法和装置。在频率合成器中，锁相环（PLL）电路基于参考频率和单位频率产生第一基本频率。第一分割模块然后划分第一基本频率以产生第二基本频率。第二分割模块将第二基本频率分割成多次，以产生单位频率和多个中频，每个频率具有与二分频率的指数比。提供第二混频器以将中频之一与单位频率混合以产生步进频率，并且第一混频器将步进频率与第一和第二基本频率中的一个频率混合以产生具有覆盖所有频率的多种频率的输出频率在超宽带（UWB）频谱中的频带。

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