专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20060120125A1 Semiconductor memory device and defect remedying method thereof 失效
公开(公告)号：US20060120125A1
公开(公告)日：2006-06-08
申请号：US11330220
申请日：2006-01-12
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C19/08
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.

92. 发明申请

US20050265092A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050265092A1
公开(公告)日：2005-12-01
申请号：US11194716
申请日：2005-08-02
申请人： Noboru Shibata , Tomoharu Tanaka
发明人： Noboru Shibata , Tomoharu Tanaka
IPC分类号： G06F12/16 , G11C7/00 , G11C11/56 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/34 , G11C29/00 , G11C29/04 , G11C29/06 , G11C29/42
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/22 , G11C16/3436 , G11C16/3454 , G11C29/70 , G11C29/832 , G11C2211/5621 , G11C2211/5641
摘要： A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.
摘要翻译：存储单元阵列具有第一和第二存储区域。第一存储区具有由地址信号选择的存储元件。第二存储区域具有由控制信号选择的存储元件。控制电路具有熔丝元件。当熔丝元件被熔断时，控制电路在第二存储区域上禁止写入和擦除中的至少一个。

93. 发明授权

US06947329B2 Method for detecting a resistive path or a predetermined potential in non-volatile memory electronic devices 有权
标题翻译：用于检测非易失性存储器电子设备中的电阻路径或预定电位的方法
公开(公告)号：US06947329B2
公开(公告)日：2005-09-20
申请号：US10675805
申请日：2003-09-30
申请人： Giovanni Campardo , Rino Micheloni
发明人： Giovanni Campardo , Rino Micheloni
IPC分类号： G11C8/02 , G11C29/00 , G11C29/02 , G11C16/04
CPC分类号： G11C29/82 , G11C29/02 , G11C29/025 , G11C29/50008 , G11C29/83 , G11C29/832
摘要： The invention relates to a method for pinpointing erase-failed memory cells and to a relevant integrated non-volatile memory device, of the programmable and electrically erasable type comprising a sectored array of memory cells arranged in rows and columns, with at least one row-decoding circuit portion per sector being supplied positive and negative voltages. This method becomes operative upon a negative erase algorithm issue, and comprises the following steps: forcing the read condition of a sector that has not been completely erased; scanning the rows of said sector to check for the presence of a spurious current indicating a failed state; finding the failed row and electrically isolating it for re-addressing the same to a redundant row provided in the same sector.
摘要翻译：本发明涉及一种用于精确定位擦除故障存储器单元的方法和可编程和电可擦除类型的相关集成非易失性存储器件，其包括以行和列布置的存储器单元的分区阵列，具有至少一个行 - 每个扇区的解码电路部分被提供正和负电压。该方法在负擦除算法问题上变得可操作，并且包括以下步骤：强制尚未被完全擦除的扇区的读取条件; 扫描所述扇区的行以检查是否存在指示故障状态的杂散电流; 发现故障行并将其电隔离以将其重新寻址到在同一扇区中提供的冗余行。

94. 发明申请

US20050018511A1 Semiconductor memory device which selectively controls a local input/output line sense amplifier 失效
标题翻译：选择性地控制本地输入/输出线路读出放大器的半导体存储器件
公开(公告)号：US20050018511A1
公开(公告)日：2005-01-27
申请号：US10892361
申请日：2004-07-16
申请人： Dong-Su Lee
发明人： Dong-Su Lee
IPC分类号： G11C7/06 , G11C7/02 , G11C11/4097 , G11C29/00
CPC分类号： G11C29/832 , G11C11/4097 , G11C29/83 , G11C29/846 , G11C2207/002
摘要： A semiconductor memory device in which a local input/output line sense amplifier may be selectively enabled or disabled. The semiconductor memory device may include a memory cell array block, a redundancy circuit, a switch unit, and/or a control unit. The memory cell array block may include a local input/output line sense amplifier that operates in response to a sense amplifier enable signal. The redundancy circuit may include a redundancy local input/output line sense amplifier that operates in response to the sense amplifier enable signal. The switch unit may selectively output data output from the local input/output line sense amplifier or the redundancy local input/output line sense amplifier, in response to a first select signal and a second select signal. If the redundancy circuit operates, the control unit may generate, in response to the second select signal, a sense amplifier operation control signal that disables the local input/output line sense amplifier. Since the semiconductor memory device selectively enables or disables the local input/output line sense amplifier, unnecessary current consumption caused due to dummy sensing is avoided.
摘要翻译：可以选择性地启用或禁用本地输入/输出线路读出放大器的半导体存储器件。半导体存储器件可以包括存储单元阵列块，冗余电路，开关单元和/或控制单元。存储单元阵列块可以包括响应于读出放大器使能信号而工作的本地输入/输出线读出放大器。冗余电路可以包括响应于读出放大器使能信号而工作的冗余本地输入/输出线路读出放大器。响应于第一选择信号和第二选择信号，开关单元可以选择性地输出从本地输入/输出线路读出放大器或冗余本地输入/输出线路读出放大器输出的数据。如果冗余电路工作，则控制单元可以响应于第二选择信号产生禁止本地输入/输出线路读出放大器的读出放大器操作控制信号。由于半导体存储器件选择性地启用或禁用本地输入/输出线路读出放大器，所以避免了由于虚拟感测引起的不必要的电流消耗。

95. 发明申请

US20040260983A1 Latched sense amplifiers as high speed memory in a memory system 失效
标题翻译：锁存读出放大器作为存储器系统中的高速存储器
公开(公告)号：US20040260983A1
公开(公告)日：2004-12-23
申请号：US10800382
申请日：2004-03-11
申请人： Monolithic System Technology, Inc.
发明人： Wing Yu Leung , Fu-Chieh Hsu
IPC分类号： H02H003/05
CPC分类号： H04L25/0272 , G06F11/006 , G06F11/10 , G06F11/1032 , G06F11/2007 , G06F12/0661 , G06F13/4077 , G11C5/04 , G11C29/006 , G11C29/08 , G11C29/48 , G11C29/76 , G11C29/808 , G11C29/81 , G11C29/832 , G11C29/88 , G11C2029/0401 , G11C2029/0411 , G11C2029/4402 , H01L22/22 , H01L27/0203 , H04L5/1461 , H04L25/026 , H04L25/028 , H04L25/029 , H04L25/0292 , Y10S257/907
摘要： A fault-tolerant, high-speed wafer scale system comprises a plurality of functional modules, a parallel hierarchical bus which is fault-tolerant to defects in an interconnect network, and one or more bus masters. This bus includes a plurality of bus lines segmented into sections and linked together by programmable bus switches and bus transceivers or repeaters in an interconnect network. By: 1) use of small block size (5 12 K bit) for the memory modules; 2) use of programmable identification register to facilitate dynamic address mapping and relatively easy incorporation of global redundancy; 3) Use of a grid structure for the bus to provide global redundancy for the interconnect network; 4) Use of a relatively narrow bus consisting of 13 signal lines to keep the total area occupied by the bus small; 5) Use of segmented bus lines connected by programmable switches and programmable bus transceivers to facilitate easy isolation of bus defects; 6) Use of special circuit for bus transceivers and asynchronous handshakes to facilitate dynamic bus configuration; 7) Use of programmable control register to facilitate run-time bus reconfiguration; 8) Use of spare bus lines to provide local redundancy for the bus; and 9) Use of spare rows and columns in the memory module to provide local redundancy, high defect tolerance in the hierarchical bus is obtained.
摘要翻译：容错的高速晶片秤系统包括多个功能模块，对互连网络中的缺陷容错的并行分层总线以及一个或多个总线主机。该总线包括分段成多个总线线路，并通过互连网络中的可编程总线开关和总线收发器或中继器连接在一起。通过：1）使用小块大小（5 12 K位）作为内存模块; 2）使用可编程标识寄存器来促进动态地址映射并相对容易地整合全局冗余; 3）使用网格结构为总线提供互联网络的全局冗余; 4）使用由13条信号线组成的较窄的总线，使总线占用的总面积较小; 5）使用由可编程开关和可编程总线收发器连接的分段总线，以便于轻松隔离总线缺陷; 6）使用专用电路进行总线收发器和异步握手，方便动态总线配置; 7）使用可编程控制寄存器，方便运行时总线重新配置; 8）使用备用总线为总线提供局部冗余; 和9）在内存模块中使用备用行和列提供局部冗余，获得分层总线中的高缺陷容限。

96. 发明申请

US20040223399A1 Method for detecting a resistive path or a predetermined potential in non-volatile memory electronic devices 有权
标题翻译：用于检测非易失性存储器电子设备中的电阻路径或预定电位的方法
公开(公告)号：US20040223399A1
公开(公告)日：2004-11-11
申请号：US10675805
申请日：2003-09-30
申请人： STMicroelectronics S.r.l.
发明人： Giovanni Campardo , Rino Micheloni
IPC分类号： G11C008/02
CPC分类号： G11C29/82 , G11C29/02 , G11C29/025 , G11C29/50008 , G11C29/83 , G11C29/832
摘要： The invention relates to a method for pinpointing erase-failed memory cells and to a relevant integrated non-volatile memory device, of the programmable and electrically erasable type comprising a sectored array of memory cells arranged in rows and columns, with at least one row-decoding circuit portion per sector being supplied positive and negative voltages. This method becomes operative upon a negative erase algorithm issue, and comprises the following steps: forcing the read condition of a sector that has not been completely erased; scanning the rows of said sector to check for the presence of a spurious current indicating a failed state; finding the failed row and electrically isolating it for re-addressing the same to a redundant row provided in the same sector.
摘要翻译：本发明涉及一种用于精确定位擦除故障存储器单元的方法和可编程和电可擦除类型的相关集成非易失性存储器件，其包括以行和列布置的存储器单元的分区阵列，具有至少一个行 - 每个扇区的解码电路部分被提供正和负电压。该方法在负擦除算法问题上变得可操作，并且包括以下步骤：强制尚未被完全擦除的扇区的读取条件; 扫描所述扇区的行以检查是否存在指示故障状态的杂散电流; 发现故障行并将其电隔离以将其重新寻址到在同一扇区中提供的冗余行。

97. 发明申请

US20040156237A1 Block select circuit in a flash memory device 失效
标题翻译：闪存设备中的块选择电路
公开(公告)号：US20040156237A1
公开(公告)日：2004-08-12
申请号：US10464666
申请日：2003-06-19
发明人： Jong Bae Jeong
IPC分类号： G11C011/34
CPC分类号： G11C29/789 , G11C8/12 , G11C16/08 , G11C29/832
摘要： Disclosed is a block select circuit in a flash memory device. The block select circuit comprises a select unit including a flash memory cell that is programmable and erasable by a given voltage condition, for outputting a block select signal depending on address signals and a state of the flash memory cell, a high-voltage pumping unit for outputting a signal to keep a given high voltage according to the block select signal and the clock signal, and a switching unit for applying a given bias to a gate select line, a word line and a source select line of a flash memory cell block according to the output signal of the high-voltage pumping unit. A given voltage is not applied to a fail block by only the operation of programming the flash memory cell of an erase state. Therefore, it is possible to process a fail block even after being packaged.
摘要翻译：公开了闪速存储器件中的块选择电路。块选择电路包括：选择单元，其包括可由可以被给定电压条件编程和擦除的闪存单元，用于根据地址信号和闪速存储单元的状态输出块选择信号;高压抽运单元，用于输出信号以根据块选择信号和时钟信号保持给定的高电压;以及切换单元，用于向闪存单元块的栅选择线，字线和源选择线施加给定偏压，所述切换单元根据到高压泵送单元的输出信号。只有对擦除状态的闪速存储器进行编程的操作，才将给定的电压施加到故障块。因此，即使在封装后也可以处理故障块。

98. 发明授权

US06657901B2 Semiconductor device formed in a rectangle region on a semiconductor substrate including a voltage generating circuit 失效
标题翻译：半导体器件形成在包括电压产生电路的半导体衬底上的矩形区域中
公开(公告)号：US06657901B2
公开(公告)日：2003-12-02
申请号：US10254980
申请日：2002-09-26
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C1604
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. A benefit of this structure in which the peripheral circuits are arranged at the center portion of the chip, is that the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
摘要翻译：一种半导体存储器件，其中外围电路布置在由纵向中心部分和横向中心部分组成的半导体芯片的交叉区域中，并且其中存储器阵列布置在由横截面划分的四个区域中。外围电路布置在芯片的中心部分的这种结构的好处是，最长的信号传输路径可以缩短到芯片尺寸的大约一半，以加快DRAM的意图。存储容量。

99. 发明申请

US20030133335A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20030133335A1
公开(公告)日：2003-07-17
申请号：US10195381
申请日：2002-07-16
申请人： Mitsubishi Denki Kabushiki Kaisha
发明人： Shigeki Ohbayashi , Yoshiyuki Ishigaki , Takahiro Yokoyama
IPC分类号： G11C029/00
CPC分类号： G11C29/83 , G11C11/4125 , G11C29/832 , H01L27/0207 , H01L27/1104
摘要： A CMOS-SRAM has a plurality of full CMOS type memory cells (1) and a capacity plate (2). The memory cells (1) are two-dimensionally arranged in the row direction and in the column direction. The capacity plate 2 adds an additional capacity to nodes ND1 and ND2 for storing data in order to reduce soft errors. The capacity plate (2) is common with the plurality of memory cells (1). The capacity plates (2) are separated by every column, that is in the row direction. The capacity plate (2) is connected to a power voltage line VDD so as to simplify the voltage supplying system. When a stand-by failure occurs in the memory cell (1) of a certain column, the memory cell (1) is replaced with a redundant memory cell.
摘要翻译： CMOS-SRAM具有多个全CMOS型存储单元（1）和容量板（2）。存储单元（1）在行方向和列方向上二维排列。容量板2为节点ND1和ND2添加额外的容量以存储数据，以便减少软错误。容量板（2）与多个存储单元（1）相同。容量板（2）由行列方向分隔。容量板（2）连接到电源电压线VDD，以简化供电系统。当在某列的存储单元（1）中发生备用故障时，存储器单元（1）被替换为冗余存储单元。

100. 发明授权

US06574159B2 Semiconductor memory device and testing method therefor 有权
公开(公告)号：US06574159B2
公开(公告)日：2003-06-03
申请号：US10137352
申请日：2002-05-03
申请人： Shigeki Ohbayashi , Yoji Kashihara , Motomu Ukita
发明人： Shigeki Ohbayashi , Yoji Kashihara , Motomu Ukita
IPC分类号： G11C2900
CPC分类号： G11C29/83 , G11C11/41 , G11C29/50 , G11C29/832 , G11C2029/5006
摘要： In a test operation for a semiconductor memory device, memory power supply lines are disconnected from a power supply node by using switch gates. Voltages of the memory power supply lines are detected using detection holding circuits. When the detected voltage is lower than a predetermined value, the corresponding memory power supply line is driven to a ground voltage level by the detection holding circuit. Thereby, a standby-current-defective but normally-operable memory cell is forced to an operation-defective state. Then, the standby-current-defective memory cell is identified, and redundancy replacement is performed thereon. Consequently, the standby current abnormality in the semiconductor memory device can be repaired.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式