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1. 发明申请

US20090268531A1 Semiconductor memory device with adjustable selected work line potential under low voltage condition 有权
公开(公告)号：US20090268531A1
公开(公告)日：2009-10-29
申请号：US12457936
申请日：2009-06-25
申请人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
发明人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
IPC分类号： G11C7/00 , G11C8/08 , G11C5/14
CPC分类号： G11C11/419 , G11C5/06 , G11C5/14 , G11C8/08 , G11C11/417 , G11C11/418
摘要： A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.

2. 发明授权

US07570525B2 Semiconductor memory device with adjustable selected work line potential under low voltage condition 有权
标题翻译：半导体存储器件，在低电压条件下具有可选择的工作线电位
公开(公告)号：US07570525B2
公开(公告)日：2009-08-04
申请号：US11492031
申请日：2006-07-25
申请人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
发明人： Koji Nii , Shigeki Ohbayashi , Yasumasa Tsukamoto , Makoto Yabuuchi
IPC分类号： G11C7/00
CPC分类号： G11C11/419 , G11C5/06 , G11C5/14 , G11C8/08 , G11C11/417 , G11C11/418
摘要： A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage.
摘要翻译：针对每个字线布置根据存储单元晶体管的阈值电压的波动来调整在选择字线时的电压电平的电平移动元件。该电平移动元件降低驱动器电源电压，并将电平移位电压发送到所选择的字线上。电平移位元件可以用用于根据存储单元晶体管的阈值电压电平来拉低字线电压的下拉元件来代替。在任一情况下，可以根据存储单元晶体管的阈值电压的波动来调整所选字线电压电平，而不使用另一电源系统。因此，电源电路不复杂，即使在低电源电压下也可以实现能够稳定地读写数据的半导体存储器件。

3. 发明授权

US07505339B2 Static semiconductor memory device allowing simultaneous writing of data into a plurality of memory cells 失效
标题翻译：静态半导体存储器件允许将数据同时写入到多个存储器单元中
公开(公告)号：US07505339B2
公开(公告)日：2009-03-17
申请号：US11451312
申请日：2006-06-13
申请人： Shigeki Ohbayashi
发明人： Shigeki Ohbayashi
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C11/413
摘要： A supply instruction signal attains the H-level before data is written into a plurality of memory cells. A P-channel MOS transistor is arranged between a power supply node and an input node. The P-channel MOS transistor is turned off to open the input node according to the supply instruction signal. In this case, a write driver discharges electric charges accumulated on the input node and electric charges accumulated on a bit line pair. However, a through-current does not flow from the power supply node to a ground node so that flow of the through-current to a CMOS inverter circuit forming each memory cell can be prevented. Accordingly, such a static semiconductor memory device can be provided that can prevent the flow of the through-current to the CMOS inverter circuit forming each memory cell when simultaneously writing data into the plurality of memory cells.
摘要翻译：在将数据写入多个存储单元之前，供给指令信号达到H电平。 P沟道MOS晶体管布置在电源节点和输入节点之间。 P沟道MOS晶体管关断，根据供电指示信号打开输入节点。在这种情况下，写入驱动器对累积在输入节点上的电荷和积累在位线对上的电荷进行放电。然而，贯通电流不会从电源节点流向接地节点，从而可以防止通过电流流向形成每个存储单元的CMOS反相器电路。因此，可以提供这样的静态半导体存储器件，当同时将数据写入到多个存储单元中时，可以防止形成每个存储单元的CMOS反相器电路的通流流动。

4. 发明授权

US06710634B2 Power on reset circuit 有权
标题翻译：上电复位电路
公开(公告)号：US06710634B2
公开(公告)日：2004-03-23
申请号：US10406312
申请日：2003-04-04
申请人： Shigeki Ohbayashi , Tadayuki Shimizu
发明人： Shigeki Ohbayashi , Tadayuki Shimizu
IPC分类号： H03L700
CPC分类号： H03K3/356008 , H03K17/223
摘要： In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.
摘要翻译：在上电复位（POR）电路中，当电源接通时，反相器的输出信号达到H电平，并且N沟道MOS晶体管导通。逆变器的输入节点的电位变为电源电压除以P沟道MOS晶体管的导电电阻值R1和N沟道MOS晶体管的导电电阻值R2的电位。假设逆变器的阈值电压为0.8V，R1：R2 = 2：3，则信号POR＃反相时的电源电压Vres为1.33V。因此，该POR电路可以可靠地利用在设计为使用具有阈值电压为0.8V的MOS晶体管的1.5V工作的产品中。

5. 发明授权

US06559489B2 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US06559489B2
公开(公告)日：2003-05-06
申请号：US09544983
申请日：2000-04-07
申请人： Ryuichi Kosugi , Shigeki Ohbayashi
发明人： Ryuichi Kosugi , Shigeki Ohbayashi
IPC分类号： H01L2972
CPC分类号： H01L21/76802 , H01L21/28512 , H01L21/76877 , H01L21/823475
摘要： A semiconductor device capable of a high-speed operation is provided. The semiconductor device is provided with low concentration impurity regions, a gate electrode formed with gate oxide film interposed between the gate electrode and a silicon substrate, an etching stopper, an interlayer insulating film having a contact hole and having an etching rate greater than that of the etching stopper, a high concentration impurity region formed by implanting an impurity into the silicon substrate through the contact hole, a plug layer filling the contact hole, and an interconnection layer.

6. 发明授权

US06388857B1 Semiconductor circuit device with improved surge resistance 失效
公开(公告)号：US06388857B1
公开(公告)日：2002-05-14
申请号：US09359124
申请日：1999-07-23
申请人： Hirotoshi Sato , Shigeki Ohbayashi
发明人： Hirotoshi Sato , Shigeki Ohbayashi
IPC分类号： H02H322
CPC分类号： H01L27/0255
摘要： Inter power supply surge voltage transmitting diode element is formed by a buried layer formed in a semiconductor substrate, a well region formed on the buried layer with its bottom portion being in contact with the buried layer, and impurity regions of mutually different conductivity types formed apart from each other at the surface of the well region. One of the impurity regions is electrically coupled to a first power supply line on which a surge voltage generates, and the other is electrically coupled to a second power supply line absorbing the surge voltage. The surge transmitting element includes a plurality of elements arranged parallel to each other between the first and second power supply lines. The second power supply line supplies the power supply voltage to an internal circuitry which consumes relatively small current.

7. 发明授权

US06373760B1 Static type semiconductor memory device adopting a redundancy system 有权
标题翻译：采用冗余系统的静态半导体存储器件
公开(公告)号：US06373760B1
公开(公告)日：2002-04-16
申请号：US09846197
申请日：2001-05-02
申请人： Shigeki Ohbayashi
发明人： Shigeki Ohbayashi
IPC分类号： G11C700
CPC分类号： G11C29/785
摘要： This SRAM includes a P-channel MOS transistor which is provided corresponding to each row and connected between one end of the memory cell power source line of the corresponding row and the line of the power source potential and which has a comparatively high conduction resistance value, and a program circuit that lets the P-channel MOS transistor become electrically non-conducted when a fuse is cut. Therefore, electric currents are prevented from flowing to a short-circuited part of the defective memory cell MC, and the leakage electric current can be restrained to a small value even if a latch-up phenomenon is generated.
摘要翻译：该SRAM包括对应于每行并连接在相应行的存储单元电源线的一端和电源电位线之间并具有较高导通电阻值的P沟道MOS晶体管，以及当熔断体被切断时使P沟道MOS晶体管变得非导通的程序电路。因此，防止电流流向故障存储单元MC的短路部分，即使产生闭锁现象，也可以将泄漏电流抑制在较小的值。

8. 发明授权

US06320802B1 Program circuit suppressing stand-by current and permitting highly reliable operation, and semiconductor memory device using the program circuit 有权
标题翻译：程序电路抑制待机电流并允许高度可靠的操作，以及使用该程序电路的半导体存储器件
公开(公告)号：US06320802B1
公开(公告)日：2001-11-20
申请号：US09785467
申请日：2001-02-20
申请人： Shigeki Ohbayashi
发明人： Shigeki Ohbayashi
IPC分类号： G11C700
CPC分类号： G11C29/785 , G11C17/18
摘要： An inverter receives a reset signal output from a reset signal generating circuit, and drives a potential level of a first internal node according to whether a fuse element is blown or not. A transfer gate is provided between the first internal node and a second internal node and drives the first internal node and the second internal node to either a conductive state or a shutdown state according to a delayed reset signal from the reset signal generating circuit. A latch circuit is provided between the second internal node and an output node, and latches a potential level of the second internal node and outputs an inverted level of the potential level of the second internal node to the output node.
摘要翻译：逆变器接收从复位信号发生电路输出的复位信号，并根据熔丝元件是否熔断来驱动第一内部节点的电位。在第一内部节点和第二内部节点之间提供传输门，并根据来自复位信号发生电路的延迟的复位信号将第一内部节点和第二内部节点驱动到导通状态或关闭状态。锁存电路设置在第二内部节点和输出节点之间，并锁存第二内部节点的电位电平，并将第二内部节点的电位电平的反相电平输出到输出节点。

9. 发明授权

US06295222B2 Semiconductor memory device with two layers of bit lines 失效
标题翻译：具有两层位线的半导体存储器件
公开(公告)号：US06295222B2
公开(公告)日：2001-09-25
申请号：US09769385
申请日：2001-01-26
申请人： Yoshiko Higashide , Shigeki Ohbayashi
发明人： Yoshiko Higashide , Shigeki Ohbayashi
IPC分类号： G11C506
CPC分类号： G11C5/063 , G11C7/18
摘要： A semiconductor memory device according to the present invention comprises, in general, a memory cell array, a plurality of first-layer and second-layer bit lines. The memory cell array includes a matrix of memory cells arranged along a line and row directions, each memory cell being formed within a memory cell region. Each of first-layer bit lines is extending along the row direction, and provided on a plurality of the memory cell regions. Each of second-layer bit lines is connected with the first-layer bit line via a connecting hole. The memory cell regions include first and second memory cell regions, the first memory cell region is provided with the connecting hole, the second memory cell region is not provided with the connecting hole. Also, at least one of the memory cells formed within the first memory cell regions is a dummy cell incapable of electrically serving as the normal memory cell.
摘要翻译：根据本发明的半导体存储器件通常包括存储单元阵列，多个第一层和第二层位线。存储单元阵列包括沿行和行方向布置的存储单元的矩阵，每个存储单元形成在存储单元区域内。每个第一层位线沿着行方向延伸，并且设置在多个存储单元区域上。每个第二层位线经由连接孔与第一层位线连接。存储单元区域包括第一和第二存储单元区域，第一存储单元区域设置有连接孔，第二存储单元区域不具有连接孔。此外，形成在第一存储单元区域内的至少一个存储单元是不能用作正常存储单元的虚拟单元。

10. 发明授权

US06229365B1 Semiconductor integrated circuit device operating stably at a plurality of power supply voltage levels 失效
标题翻译：半导体集成电路器件在多个电源电压电平下稳定地工作
公开(公告)号：US06229365B1
公开(公告)日：2001-05-08
申请号：US08982033
申请日：1997-12-01
申请人： Masayuki Iketani , Shigeki Ohbayashi
发明人： Masayuki Iketani , Shigeki Ohbayashi
IPC分类号： H03K512
CPC分类号： G11C7/1078 , H03K19/018585
摘要： At the last stage of a level converter that provides an internal signal to an internal signal output node, MOS transistors that are rendered conductive alternatively are provided as current source transistors. These additional MOS transistors are selectively rendered conductive according to the voltage level of, for example, a bonding pad. The charging/discharging current towards the internal node can be adjusted. Accordingly, the rising time and falling time of the internal signal can be constantly made equal. Thus an input/output circuit that can provide a signal at a proper timing even when the operating environment such as the system power supply voltage changes can be implemented.
摘要翻译：在向内部信号输出节点提供内部信号的电平转换器的最后阶段，作为电流源晶体管提供替代导通的MOS晶体管。这些附加MOS晶体管根据例如焊盘的电压电位有选择地导通。可以调节朝向内部节点的充电/放电电流。因此，内部信号的上升时间和下降时间可以恒定地相等。因此，即使可以实现诸如系统电源电压变化的操作环境，也可以在适当的定时提供信号的输入/输出电路。

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