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91. 发明授权

US07864618B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07864618B2
公开(公告)日：2011-01-04
申请号：US12137802
申请日：2008-06-12
申请人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
发明人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
IPC分类号： G11C8/00
CPC分类号： G11C5/025 , G11C29/1201 , G11C29/26 , G11C29/48
摘要： A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip.
摘要翻译：半导体存储器件包括多个存储体，每个存储体由在纵向方向上串联排列的多个存储单元阵列构成，其中每个存储单元阵列包括多个存储单元，并且其中存储单元阵列银行被集体地聚集成多个块，每个块包括与多个DQ焊盘相关联的在垂直方向上排列的存储单元阵列。 DQ垫布置在块附近。在存储单元和DQ垫之间基本上设置相同的距离，以便相对于所有DQ焊盘减少访问时间的分散，从而实现半导体存储器件中的高速访问。在芯片的中心区域，IO线的布线区域减小。

92. 发明授权

US07839708B2 Semiconductor apparatus and testing method using different internal voltages to output binary signals 有权
标题翻译：半导体装置和使用不同内部电压的测试方法来输出二进制信号
公开(公告)号：US07839708B2
公开(公告)日：2010-11-23
申请号：US11662705
申请日：2006-06-27
申请人： Takao Jinzai
发明人： Takao Jinzai
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G01R31/2822 , G01R31/2884 , G01R31/308 , G11C2029/0401
摘要： A semiconductor apparatus, configured to operate on different internal voltages generated from electromagnetic waves received via an antenna, to extract a command and data from the received electromagnetic waves, and to operate according to the extracted command, includes internal circuitry configured to generate and output binary signals according to a command input from the outside in a test operation for performing a predetermined test; and output circuits corresponding to some or all of the internal voltages and configured to convert the binary signals output from the internal circuitry into binary signals having same voltages as the corresponding internal voltages and to output the converted binary signals to the outside.
摘要翻译：一种半导体装置，被配置为对从经由天线接收的电磁波产生的不同的内部电压进行操作，以从所接收的电磁波中提取命令和数据，并根据所提取的命令进行操作，所述半导体装置包括内部电路，其被配置为生成和输出二进制在进行预定测试的测试操作中根据来自外部的命令输入信号; 和对应于部分或全部内部电压的输出电路，并配置为将从内部电路输出的二进制信号转换成具有与相应的内部电压相同的电压的二进制信号，并将转换的二进制信号输出到外部。

93. 发明授权

US07839699B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07839699B2
公开(公告)日：2010-11-23
申请号：US12050386
申请日：2008-03-18
申请人： Tomoki Higashi , Takashi Ohsawa
发明人： Tomoki Higashi , Takashi Ohsawa
IPC分类号： G11C7/00 , G11C7/02 , G11C5/14
CPC分类号： H01L29/7841 , G11C7/1051 , G11C7/1057 , G11C7/1069 , G11C11/404 , G11C11/4093 , G11C11/4096 , G11C29/1201 , G11C29/48 , G11C29/50 , G11C2029/0403 , G11C2029/5006 , G11C2211/4016
摘要： This disclosure concerns a semiconductor memory device comprising: a memory cell array having memory cells arrayed two-dimensionally; word lines connected to the memory cells of rows of the memory cell array; bit lines connected to the memory cells of columns of the memory cell array; sense amplifiers connected to the bit lines, and detecting data stored in the memory cells; a test pad passing a predetermined reference current from a power source, and transmitting a reference voltage based on the reference current; and test circuits connected between the power source and the test pad and intervening between the power source and the bit lines, the test circuits passing test currents according to the reference voltage via the bit lines.
摘要翻译：本公开涉及一种半导体存储器件，包括：具有二维排列的存储单元的存储单元阵列; 连接到存储单元阵列的行的存储单元的字线; 连接到存储单元阵列的列的存储单元的位线; 连接到位线的感测放大器，以及检测存储在存储单元中的数据; 测试垫，其从电源通过预定的参考电流，并且基于所述参考电流传输参考电压; 以及连接在电源和测试焊盘之间并且插入电源和位线之间的测试电路，测试电路经由位线根据参考电压使测试电流通过。

94. 发明授权

US07831871B2 Testing embedded memories in an integrated circuit 有权
标题翻译：在集成电路中测试嵌入式存储器
公开(公告)号：US07831871B2
公开(公告)日：2010-11-09
申请号：US12400664
申请日：2009-03-09
申请人： Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
发明人： Don E. Ross , Xiaogang Du , Wu-Tung Cheng , Joseph C. Rayhawk
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/1201 , G11C29/48 , G11C2029/0401 , G11C2029/0405 , G11C2029/3202
摘要： Various new and non-obvious apparatus and methods for testing embedded memories in an integrated circuit are disclosed. One of the disclosed embodiments is an apparatus for testing an embedded memory in an integrated circuit. This exemplary embodiment comprises input logic that includes one or more memory-input paths coupled to respective memory inputs of the embedded memory, a memory built-in self-test (MBIST) controller, and at least one scan cell coupled between the input logic and the MBIST controller. The scan cell of this embodiment is selectively operable in a memory-test mode and a system mode. In memory-test mode, the scan cell can apply memory-test data to the memory inputs along the memory-input paths of the integrated circuit. Any of the disclosed apparatus can be designed, simulated, and/or verified (and any of the disclosed methods can be performed) in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool.
摘要翻译：公开了用于在集成电路中测试嵌入式存储器的各种新的和非显而易见的装置和方法。所公开的实施例之一是用于测试集成电路中的嵌入式存储器的装置。该示例性实施例包括输入逻辑，其包括耦合到嵌入式存储器的相应存储器输入的一个或多个存储器输入路径，存储器内置自检（MBIST）控制器，以及耦合在输入逻辑和 MBIST控制器。本实施例的扫描单元可选择性地在存储器测试模式和系统模式下工作。在存储器测试模式下，扫描单元可以将存储器测试数据沿集成电路的存储器输入路径应用于存储器输入。在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中，可以设计，模拟和/或验证任何公开的装置（并且可以执行任何公开的方法）。

95. 发明申请

US20100257417A1 COMPRESSING TEST RESPONSES USING A COMPACTOR 有权
标题翻译：使用压缩机压缩测试响应
公开(公告)号：US20100257417A1
公开(公告)日：2010-10-07
申请号：US12818941
申请日：2010-06-18
申请人： Janusz Rajski , Jerzy Tyszer , Chen Wang , Grzegorz Mrugalski , Artur Pogiel
发明人： Janusz Rajski , Jerzy Tyszer , Chen Wang , Grzegorz Mrugalski , Artur Pogiel
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318566 , G01R31/31703 , G01R31/318536 , G01R31/318583 , G01R31/31921 , G11C29/40 , G11C29/48 , G11C2029/3202
摘要： The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.
摘要翻译：本公开描述了用于压缩集成电路中的测试结果的压实机的实施例以及用于使用和设计这些实施例的方法。所公开的压实机可以例如用作任何基于扫描的设计的一部分。此外，任何公开的压实机可以在诸如电子设计自动化（“EDA”）软件工具的计算机执行的应用中被设计，模拟和/或验证。还描述了在公开的压实机实施例中用于诊断故障的方法的实施例。

96. 发明申请

US20100195428A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100195428A1
公开(公告)日：2010-08-05
申请号：US12695364
申请日：2010-01-28
申请人： Tomonori HAYASHI
发明人： Tomonori HAYASHI
IPC分类号： G11C7/00
CPC分类号： G11C29/48 , G11C29/1201
摘要： A semiconductor device comprises a plurality of terminals, a plurality of drive units corresponding to the plurality of terminals, and a data control unit. The data control unit outputs parallel data applied to the plurality of terminals to the plurality of drive unit in a normal operation mode, and converts serial data applied to a particular terminal, which is one of the plurality of terminals, to parallel data, and outputs the parallel data to which the serial data applied to the particular terminal is converted to the plurality of drive units in a test mode.
摘要翻译：半导体器件包括多个端子，对应于多个端子的多个驱动单元和数据控制单元。数据控制单元在正常操作模式下向多个驱动单元输出应用于多个终端的并行数据，并且将应用于作为多个终端之一的特定终端的串行数据转换为并行数据，并输出在测试模式中将应用于特定终端的串行数据的并行数据转换为多个驱动单元。

97. 发明授权

US07751265B2 Semiconductor device including a plurality of memory units and method of testing the same 失效
标题翻译：包括多个存储单元的半导体器件及其测试方法
公开(公告)号：US07751265B2
公开(公告)日：2010-07-06
申请号：US12001230
申请日：2007-12-10
申请人： Jin Ho So , Kwang Hyun Kim , Chan Jin Park
发明人： Jin Ho So , Kwang Hyun Kim , Chan Jin Park
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/1201 , G11C2029/2602
摘要： In a semiconductor device including a plurality of memory units and a method of testing the same, the semiconductor device includes a plurality of memory units each comprising a plurality of input lines; and an input unit configured to provide a plurality of test signals to the input lines, respectively, included in each of the memory units in response to a test enable signal. A data input/output unit can be configured to receive Z-bit data from test equipment and to distribute the Z-bit data to the plurality of memory units in response to the test enable signal, where Z is a natural number. The data input/output unit outputs K-bit data, which are output from each of the plurality of memory units, through data input/output lines included in the plurality of memory units in response to the test enable signal, where K≦Z and K is a natural number.
摘要翻译：在包括多个存储单元的半导体器件及其测试方法中，半导体器件包括多个存储器单元，每个存储器单元包括多条输入线; 以及输入单元，被配置为响应于测试使能信号而分别将包括在每个存储器单元中的输入线提供多个测试信号。数据输入/输出单元可被配置为从测试设备接收Z位数据，并且响应于测试使能信号将Z位数据分配给多个存储器单元，其中Z是自然数。数据输入/输出单元响应于测试使能信号，通过包括在多个存储器单元中的数据输入/输出线输出从多个存储器单元中的每一个输出的K位数据，其中K＆nlE; Z和 K是自然数。

98. 发明授权

US07743291B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07743291B2
公开(公告)日：2010-06-22
申请号：US11825240
申请日：2007-07-05
申请人： Nobuo Yamamoto
发明人： Nobuo Yamamoto
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C7/1078 , G11C7/1087 , G11C11/401 , G11C29/1201 , G11C2029/2602 , G11C2207/108
摘要： A semiconductor memory device includes a memory cell array, a plurality of data input/output terminals, a plurality of signal paths for writing data supplied to the data input/output terminals to the memory cell array in parallel, a plurality of latch circuits temporarily holding the data on the signal paths, respectively, and a selector selectively supplying the data to the latch circuits from a test data terminal during a test operation. The data can be thereby supplied from the test data terminal to the latch circuits in parallel during the test operation. The number of terminals used at an operation test can be, therefore, greatly decreased.
摘要翻译：半导体存储器件包括存储单元阵列，多个数据输入/输出端子，用于将提供给数据输入/输出端子的数据并行写入存储单元阵列的多个信号路径，多个锁存电路暂时保持信号路径上的数据以及在测试操作期间从测试数据终端选择性地将数据提供给锁存电路的选择器。因此，可以在测试操作期间将数据从测试数据终端并行提供给锁存电路。因此，在操作测试中使用的端子的数量可以大大降低。

99. 发明授权

US07742349B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07742349B2
公开(公告)日：2010-06-22
申请号：US12164045
申请日：2008-06-28
申请人： Chun-Seok Jeong , Beom-Ju Shin
发明人： Chun-Seok Jeong , Beom-Ju Shin
IPC分类号： G11C7/00
CPC分类号： G11C29/14 , G11C7/1045 , G11C29/1201 , G11C29/12015 , G11C29/48
摘要： A circuit can control a bit rate of information output from a multi-purpose register (MPR) of a semiconductor memory device in a test mode, thereby reducing current consumption for outputting information in a multi-purpose register (MPR). The semiconductor memory device includes a multi-purpose register configured separately to store a plurality of information, and to control a bit rate of the stored information in a test mode, each of the information having multiple bits, and a connection selector configured selectively to connect an output terminal of the multi-purpose register to one of a number of global lines according to an operation mode.
摘要翻译：电路可以在测试模式中控制从半导体存储器件的多用途寄存器（MPR）输出的信息的比特率，从而减少用于在多用途寄存器（MPR）中输出信息的电流消耗。半导体存储器件包括分别配置以存储多个信息的多用途寄存器，并且在测试模式下控制所存储的信息的比特率，每个信息具有多个位，以及连接选择器，其被选择性地配置为连接根据操作模式将多功能寄存器的输出端子连接到多条全局线路之一。

100. 发明申请

US20100148815A1 TEST APPARATUS 失效
标题翻译：测试仪器
公开(公告)号：US20100148815A1
公开(公告)日：2010-06-17
申请号：US12618619
申请日：2009-11-13
申请人： Makoto TABATA
发明人： Makoto TABATA
IPC分类号： G01R31/02
CPC分类号： G11C29/56 , G11C29/48 , G11C2029/5602 , G11C2029/5606
摘要： Provided is a test apparatus that tests a device under test having a test function for sequentially outputting, from a single test terminal, signals that would be output from a plurality of terminals, the test apparatus comprising: a test section that supplies the device under test with a test signal and receives signals that are sequentially output from the test terminal in response to the test signal; an identifying section that identifies a correspondence between each signal sequentially received by the test section and a signal that would be output from one of the terminals of the device under test; and a counting section that counts a number of signals judged to be unacceptable from among the signals sequentially received by the test section for each terminal of the device under test, based on the correspondence identified by the identifying section.
摘要翻译：提供了一种测试装置，其具有测试功能，用于从单个测试终端顺序地输出将从多个终端输出的信号，该测试装置包括：供给被测设备的测试部分具有测试信号并接收响应于测试信号从测试终端顺序地输出的信号; 标识部分，其识别由测试部分顺序接收的每个信号与将从被测设备的一个终端输出的信号之间的对应关系; 以及计数部，其基于由识别部识别的对应关系，对从被测设备的每个终端按测试部分顺序接收的信号中判定为不可接受的信号数进行计数。

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