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1. 发明授权

US07864618B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07864618B2
公开(公告)日：2011-01-04
申请号：US12137802
申请日：2008-06-12
申请人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
发明人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
IPC分类号： G11C8/00
CPC分类号： G11C5/025 , G11C29/1201 , G11C29/26 , G11C29/48
摘要： A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip.
摘要翻译：半导体存储器件包括多个存储体，每个存储体由在纵向方向上串联排列的多个存储单元阵列构成，其中每个存储单元阵列包括多个存储单元，并且其中存储单元阵列银行被集体地聚集成多个块，每个块包括与多个DQ焊盘相关联的在垂直方向上排列的存储单元阵列。 DQ垫布置在块附近。在存储单元和DQ垫之间基本上设置相同的距离，以便相对于所有DQ焊盘减少访问时间的分散，从而实现半导体存储器件中的高速访问。在芯片的中心区域，IO线的布线区域减小。

2. 发明申请

US20090003107A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090003107A1
公开(公告)日：2009-01-01
申请号：US12145240
申请日：2008-06-24
申请人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
发明人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
IPC分类号： G11C7/12
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1069
摘要： A semiconductor device includes a column decoder that generates a column selecting signal that selects any of a plurality of bit line pairs to which memory cells are connected according to a column address that is input; a bit line selecting switch that connects by the column selecting signal any of a plurality of bit line pairs and a data I/O line pair that outputs data that has been read from a memory cell to the outside; a data amplifier that amplifies a voltage differential of a data I/O line pair and outputs data that has been read to an output buffer; a data I/O line switch that is provided in the data I/O lines; an I/O line precharge circuit that precharges a data I/O line pair that is not on the side of the data amplifier; and an amplifier precharge circuit that precharges a data I/O line pair that is on the side of the data amplifier.
摘要翻译：半导体器件包括：列解码器，根据输入的列地址，生成列选择信号，该列选择信号选择存储单元连接到的多个位线对; 通过列选择信号连接多个位线对的位线选择开关和将从存储单元读出的数据输出到外部的数据I / O线对; 数据放大器，其放大数据I / O线对的电压差，并将已读取的数据输出到输出缓冲器; 在数据I / O线路中提供的数据I / O线路开关; 对不在数据放大器一侧的数据I / O线对进行预充电的I / O线路预充电电路; 以及对数据放大器侧面的数据I / O线对进行预充电的放大器预充电电路。

3. 发明申请

US20090003026A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090003026A1
公开(公告)日：2009-01-01
申请号：US12137802
申请日：2008-06-12
申请人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
发明人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
IPC分类号： G11C5/02 , G11C8/00
CPC分类号： G11C5/025 , G11C29/1201 , G11C29/26 , G11C29/48
摘要： A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip.
摘要翻译：半导体存储器件包括多个存储体，每个存储体由在纵向方向上串联排列的多个存储单元阵列构成，其中每个存储单元阵列包括多个存储单元，并且其中存储单元阵列银行被集体地聚集成多个块，每个块包括与多个DQ焊盘相关联的在垂直方向上排列的存储单元阵列。 DQ垫布置在块附近。在存储单元和DQ垫之间基本上设置相同的距离，以便相对于所有DQ焊盘减少访问时间的分散，从而实现半导体存储器件中的高速访问。在芯片的中心区域，IO线的布线区域减小。

4. 发明授权

US07796453B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07796453B2
公开(公告)日：2010-09-14
申请号：US12145240
申请日：2008-06-24
申请人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
发明人： Yoshiro Riho , Hayato Oishi , Yoshinori Haraguchi , Yoshinori Matsui
IPC分类号： G11C11/00
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1069
摘要： A semiconductor device includes a column decoder that generates a column selecting signal that selects any of a plurality of bit line pairs to which memory cells are connected according to a column address that is input; a bit line selecting switch that connects by the column selecting signal any of a plurality of bit line pairs and a data I/O line pair that outputs data that has been read from a memory cell to the outside; a data amplifier that amplifies a voltage differential of a data I/O line pair and outputs data that has been read to an output buffer; a data I/O line switch that is provided in the data I/O lines; an I/O line precharge circuit that precharges a data I/O line pair that is not on the side of the data amplifier; and an amplifier precharge circuit that precharges a data I/O line pair that is on the side of the data amplifier.
摘要翻译：半导体器件包括：列解码器，根据输入的列地址，生成列选择信号，该列选择信号选择存储单元连接到的多个位线对; 通过列选择信号连接多个位线对的位线选择开关和将从存储单元读出的数据输出到外部的数据I / O线对; 数据放大器，其放大数据I / O线对的电压差，并将已读取的数据输出到输出缓冲器; 在数据I / O线路中提供的数据I / O线路开关; 对不在数据放大器一侧的数据I / O线对进行预充电的I / O线路预充电电路; 以及对数据放大器侧面的数据I / O线对进行预充电的放大器预充电电路。

5. 发明授权

US08660189B2 Generation apparatus generating a stream including a flag, mode information and an encoded picture, and a generation method performing the same 有权
标题翻译：产生包括标志，模式信息和编码图像的流的生成装置，以及执行该流的生成方法
公开(公告)号：US08660189B2
公开(公告)日：2014-02-25
申请号：US12817344
申请日：2010-06-17
申请人： Tadamasa Toma , Shinya Kadono , Masayasu Iguchi , Tomoyuki Okada , Yoshinori Matsui , Satoshi Kondo , Hiroshi Yahata , Wataru Ikeda
发明人： Tadamasa Toma , Shinya Kadono , Masayasu Iguchi , Tomoyuki Okada , Yoshinori Matsui , Satoshi Kondo , Hiroshi Yahata , Wataru Ikeda
IPC分类号： H04N11/02
CPC分类号： H04N9/8042 , G11B27/3027 , G11B27/329 , G11B2220/2541 , H04N5/85 , H04N9/8063 , H04N9/8205 , H04N9/8227 , H04N19/13 , H04N19/179 , H04N19/61
摘要： A moving image encoding method of encoding a moving image while switching between variable-length encoding schemes. In this method, a continuous unit to be continuously reproduced is determined (S5201), a stream is generated by encoding the moving image without switching between variable-length encoding schemes in the continuous unit (S5202), and management information is generated that includes a first flag information indicating that a variable-length encoding scheme is fixed in the continuous unit (S5204, and S5205).
摘要翻译：一种在可变长度编码方案之间切换的同时对运动图像进行编码的运动图像编码方法。在该方法中，确定要连续重放的连续单元（S5201），通过对运动图像进行编码而不在连续单元中的可变长度编码方案之间进行切换来生成流（S5202），生成包括指示可变长度编码方案在连续单元中固定的第一标志信息（S5204和S5205）。

6. 发明授权

US08271740B2 Multiport memory and information processing system 有权
标题翻译：多端口内存和信息处理系统
公开(公告)号：US08271740B2
公开(公告)日：2012-09-18
申请号：US12411974
申请日：2009-03-26
申请人： Seiji Miura , Yoshinori Matsui , Kazuhiko Abe , Shoji Kaneko
发明人： Seiji Miura , Yoshinori Matsui , Kazuhiko Abe , Shoji Kaneko
IPC分类号： G06F12/00
CPC分类号： G11C7/1075 , G06F13/1663
摘要： In an information processing system, a plurality of information processing devices CHIP0 and CHIP1 are connected to multiport memory MPMEM0 that has a plurality of ports, and memory areas in multiport memory MPMEM0 can be altered to memory areas occupied by particular ports and memory areas shared by a plurality of ports. At such times, immediately after the occurrence of a request from a port, the status of this request may be supplied from other ports.
摘要翻译：在信息处理系统中，多个信息处理装置CHIP0和CHIP1连接到具有多个端口的多端口存储器MPMEM0，并且多端口存储器MPMEM0中的存储区域可以被改变为由特定端口和存储区域所占用的存储区域多个端口。在这样的时刻，在从端口发出请求之后，可以从其他端口提供该请求的状态。

7. 发明授权

US08078581B2 Storage system and remote copy control method 有权
标题翻译：存储系统和远程复制控制方法
公开(公告)号：US08078581B2
公开(公告)日：2011-12-13
申请号：US12029139
申请日：2008-02-11
申请人： Kensuke Amaki , Kenichi Oyamada , Takeyuki Imazu , Yoshinori Matsui
发明人： Kensuke Amaki , Kenichi Oyamada , Takeyuki Imazu , Yoshinori Matsui
IPC分类号： G06F7/00
CPC分类号： G06F11/2074 , G06F11/2064 , G06F11/2082 , G06F2201/855
摘要： A plurality of second groups respectively including one or more second volumes are configured in correspondence with each of the first groups of a remote copy source in a remote copy destination, journals are acquired from the first storage apparatus periodically and in the order the journals were created for each of the configured second groups, and the acquired journals are reflected in the corresponding second volume in the corresponding second group. In addition, the latest time stamp of each of the second groups containing the journals retained in the second volume in an unreflected state is compared, the time difference of the latest and oldest time stamps is detected, and prescribed control processing is executed for acquiring the journals regarding the second group with the oldest time stamp in preference to the journals regarding other second groups when the time difference exceeds a preset threshold value.
摘要翻译：分别包括一个或多个第二卷的多个第二组被配置为与远程复制目的地中的远程复制源的第一组中的每一个相对应，周期性地从第一存储装置获取期刊，并且按照创建的期刊的顺序对于每个配置的第二组，并且所获取的日志被反映在相应的第二组中的对应的第二卷中。另外，比较包含保持在未反射状态的第二卷中的期刊的每个第二组的最新时间戳，检测最新和最旧的时间戳的时间差，并且执行规定的控制处理以获取当时间差超过预设阈值时，关于具有最早时间戳的第二组的期刊优先于关于其他第二组的期刊。

8. 发明授权

US08072492B2 Mobile terminal device 有权
标题翻译：移动终端设备
公开(公告)号：US08072492B2
公开(公告)日：2011-12-06
申请号：US10594147
申请日：2005-05-17
申请人： Satoshi Kondo , Hisao Sasai , Takahiro Nishi , Tadamasa Toma , Toshiyasu Sugio , Yoshinori Matsui
发明人： Satoshi Kondo , Hisao Sasai , Takahiro Nishi , Tadamasa Toma , Toshiyasu Sugio , Yoshinori Matsui
IPC分类号： H04N7/18 , H04M1/00
CPC分类号： H04N5/76 , H04N5/445 , H04N21/4122 , H04N21/41407 , H04N21/4227 , H04N21/4316 , H04N21/4333 , H04N21/44008 , H04N21/478 , H04N21/4786 , H04N21/4882 , H04N21/812
摘要： To provide a mobile terminal device which can perform an operation reflecting the intention of a user when an event, such as the arrival of an incoming phone call or an email, occurs while a television broadcast is being displayed, and which can also improve the operability. A mobile terminal device is composed of: a TV reception unit which receives a television broadcast signal; an output control unit which controls outputs of video and audio of the television broadcast, auxiliary information of the television broadcast, the email, audio of the phone call, and video and audio of a video phone call, to a first display unit, a second display unit, and an audio reproduction unit; a recording control unit which records a television broadcast program onto a recording medium; a reproduction control unit which reproduces the television broadcast program recorded on the recording medium; a control unit which controls an operation performed when the email or the phone call is receives while the television broadcast is being displayed; and an unfold/fold detection unit which detects whether the mobile terminal device is folded or unfolded.
摘要翻译：为了提供一种移动终端设备，当在显示电视广播的同时，当诸如到来的电话呼叫或电子邮件等事件发生时，可以执行反映用户意图的操作，并且还可以提高可操作性。一种移动终端设备包括：接收电视广播信号的电视接收单元; 输出控制单元，其将电视广播的视频和音频输出，电视广播的辅助信息，电话，电话的音频以及视频电话的视频和音频的输出控制到第一显示单元，第二显示单元显示单元和音频再现单元; 记录控制单元，其将电视广播节目记录到记录介质上; 再现控制单元，其再现记录在记录介质上的电视广播节目; 控制单元，其控制在显示电视广播时接收到电子邮件或电话呼叫时执行的操作; 以及展开/折叠检测单元，其检测移动终端设备是否被折叠或展开。

9. 发明申请

US20110261640A1 Semiconductor memory device and data processing system including the semiconductor memory device 有权
标题翻译：包括半导体存储器件的半导体存储器件和数据处理系统
公开(公告)号：US20110261640A1
公开(公告)日：2011-10-27
申请号：US13067849
申请日：2011-06-29
申请人： Yoshinori Matsui
发明人： Yoshinori Matsui
IPC分类号： G11C8/16 , G11C8/10
CPC分类号： G11C7/1075
摘要： A semiconductor device, includes a first memory cell array, a second memory cell array, a command decoder configured to produce a transfer command to transfer a data stored in a first area of the first memory cell array to a second area of the second memory cell array, when receiving a read command to the first memory cell array and sequentially a write command to the second cell memory array, a first address generator configured to produce a first internal address for designating the first area of the first memory cell array when receiving the transfer command from the command decoder; and a second address generator configured to produce a second internal address for designating the second area of the second memory cell array when receiving the transfer command from the command decoder.
摘要翻译：一种半导体器件，包括第一存储单元阵列，第二存储单元阵列，命令解码器，被配置为产生将存储在第一存储单元阵列的第一区域中的数据传送到第二存储单元的第二区域的传送命令阵列，当接收到第一存储单元阵列的读取命令并且顺序地向第二单元存储器阵列写入命令时，第一地址生成器被配置为产生用于指定第一存储单元阵列的第一区域的第一内部地址，命令解码器传输命令; 以及第二地址发生器，被配置为当从命令解码器接收到传送命令时，产生用于指定第二存储单元阵列的第二区域的第二内部地址。

10. 发明授权

US07978557B2 Semiconductor memory device and data processing system including the semiconductor memory device 有权
标题翻译：包括半导体存储器件的半导体存储器件和数据处理系统
公开(公告)号：US07978557B2
公开(公告)日：2011-07-12
申请号：US12318731
申请日：2009-01-07
申请人： Yoshinori Matsui
发明人： Yoshinori Matsui
IPC分类号： G11C7/00
CPC分类号： G11C7/1075
摘要： A semiconductor device that includes a plurality of memory cell arrays, a plurality of ports, a plurality of internal address generating circuits, and a controller. The plurality of internal address generating circuits may generate first and second internal addresses of first and second memory cell arrays of the plurality of memory cell arrays. The first internal address may designate a first area of the first memory cell array. The second internal address may designate a second area of the second memory cell array. The controller reads a series of data from the first area sequentially and writes the series of read data into the second area sequentially without transferring the series of read data to the plurality of ports.
摘要翻译：一种半导体器件，包括多个存储单元阵列，多个端口，多个内部地址生成电路和控制器。多个内部地址产生电路可以生成多个存储单元阵列中的第一和第二存储单元阵列的第一和第二内部地址。第一内部地址可以指定第一存储单元阵列的第一区域。第二内部地址可以指定第二存储单元阵列的第二区域。控制器顺序地从第一区域读取一系列数据，并将读取数据序列顺序地写入第二区域，而不将该系列读取数据传送到多个端口。

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