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91. 发明申请

US20120173811A1 Method and Apparatus for Delaying Write Operations 审中-公开
标题翻译：延迟写入操作的方法和装置
公开(公告)号：US20120173811A1
公开(公告)日：2012-07-05
申请号：US13421753
申请日：2012-03-15
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An apparatus for controlling a dynamic random access memory (DRAM), the apparatus comprising an interface to transmit to the DRAM a first code to indicate that first data is to be written to the DRAM. The first code is to be sampled by the DRAM and held by the DRAM for a first period of time before it is issued inside the DRAM. The interface is further to transmit the first data that is to be sampled by the DRAM after a second period of time has elapsed from when the first code is sampled by the DRAM. The interface is further to transmit a second code, different from the first code, to indicate that second data is to be read from the DRAM. The second code is to be sampled by the DRAM on one or more edges of the external clock signal.
摘要翻译：一种用于控制动态随机存取存储器（DRAM）的装置，该装置包括用于向DRAM发送第一代码以指示要将第一数据写入DRAM的接口。第一代码将由DRAM采样并由DRAM在DRAM发出之前的第一时间段内保持。该接口在从DRAM的第一代码被采样起经过了第二时间段之后，进一步发送由DRAM采样的第一数据。该接口还用于发送与第一代码不同的第二代码，以指示要从DRAM读取第二数据。第二个代码由外部时钟信号的一个或多个边缘上的DRAM采样。

92. 发明申请

US20120147678A1 Buffering Systems For Accessing Multiple Layers Of Memory In Integrated Circuits 审中-公开
标题翻译：用于在集成电路中访问多层存储器的缓冲系统
公开(公告)号：US20120147678A1
公开(公告)日：2012-06-14
申请号：US13401661
申请日：2012-02-21
申请人： ROBERT NORMAN
发明人： ROBERT NORMAN
IPC分类号： G11C7/10
CPC分类号： G11C7/1006 , G06F13/1668 , G11C5/025 , G11C7/1012 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C2207/2218
摘要： Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.
摘要翻译：本发明的实施例一般涉及数据存储和计算机存储器，更具体地，涉及用于访问实现例如第三维存储器技术的多层存储器中的存储器的系统，集成电路和方法。在具体实施例中，集成电路被配置为实现写入缓冲器以访问多层存储器。例如，集成电路可以包括设置在多层存储器中的存储单元。在一个实施例中，存储器单元可以是第三维存储器单元。集成电路还可以包括可以与写入缓冲器不同的读取缓冲器。在至少一个实施例中，写入缓冲器的大小可以作为写周期的函数。每层存储器可以包括多个两端存储元件，其在不存在功率的情况下保存存储的数据，并将数据存储为多个导电率分布。

93. 发明授权

US08154932B2 Increasing efficiency of memory accesses by selectively introducing a relative delay between the time that write addresses are provided to the memory and the time that write data is provided to the memory 有权
标题翻译：通过在写入地址被提供给存储器的时间和向存储器提供写入数据的时间之间选择性地引入相对延迟来提高存储器访问的效率
公开(公告)号：US08154932B2
公开(公告)日：2012-04-10
申请号：US13051038
申请日：2011-03-18
申请人： J. Thomas Pawlowski
发明人： J. Thomas Pawlowski
IPC分类号： G06F12/00
CPC分类号： G06F12/0207 , G06F12/0607 , G11C7/1039 , G11C7/1072 , G11C11/4076 , G11C2207/2218 , G11C2207/229
摘要： Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access.
摘要翻译：提供了用于减少多组存储器件中的连续写入和读取访问之间的延迟的系统和方法。计算机电路修改写访问的地址和数据之间的相对定时，减少连续写入和读取访问之间的延迟。与这些计算机电路接口的存储器件使用发布的写入访问，以在处理写入访问之前有效地将修改的相对定时返回到其原始时序。

94. 发明授权

US08120970B2 Buffering systems for accessing multiple layers of memory in integrated circuits 有权
标题翻译：用于在集成电路中访问多层存储器的缓冲系统
公开(公告)号：US08120970B2
公开(公告)日：2012-02-21
申请号：US13134734
申请日：2011-06-14
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C7/10
CPC分类号： G11C7/1006 , G06F13/1668 , G11C5/025 , G11C7/1012 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C2207/2218
摘要： Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.
摘要翻译：本发明的实施例一般涉及数据存储和计算机存储器，更具体地，涉及用于访问实现例如第三维存储器技术的多层存储器中的存储器的系统，集成电路和方法。在具体实施例中，集成电路被配置为实现写入缓冲器以访问多层存储器。例如，集成电路可以包括设置在多层存储器中的存储单元。在一个实施例中，存储器单元可以是第三维存储器单元。集成电路还可以包括可以与写入缓冲器不同的读取缓冲器。在至少一个实施例中，写入缓冲器的大小可以作为写周期的函数。每层存储器可以包括多个两端存储元件，其在不存在功率的情况下保存存储的数据，并将数据存储为多个导电率分布。

95. 发明授权

US08019958B2 Memory write signaling and methods thereof 有权
标题翻译：存储器写入信令及其方法
公开(公告)号：US08019958B2
公开(公告)日：2011-09-13
申请号：US12875483
申请日：2010-09-03
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarre , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarre , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.
摘要翻译：在控制存储器件的方法中，以下是通过第一组互连资源传送的：指定一行存储器单元的激活的第一命令; 指定写操作的第二命令，其中写数据被写入行; 指定在写入数据写入之后是否发生预充电的一点; 以及指定是否将为写入操作发布数据掩码信息的代码。如果代码指定信息将被发出，则在传送代码之后，通过第一组互连资源传送指定是否选择性地写入写入数据的部分的信息。要写入与写入操作相关的写入数据通过与第一组互连资源分开的第二组互连资源传送。

96. 发明授权

US07961527B2 Buffering systems for accessing multiple layers of memory in integrated circuits 有权
公开(公告)号：US07961527B2
公开(公告)日：2011-06-14
申请号：US12657385
申请日：2010-01-19
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： G11C7/10
CPC分类号： G11C7/1006 , G06F13/1668 , G11C5/025 , G11C7/1012 , G11C7/1078 , G11C7/1084 , G11C7/1096 , G11C2207/2218
摘要： Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

97. 发明授权

US07870357B2 Memory system and method for two step memory write operations 有权
标题翻译：用于两步存储器写操作的存储器系统和方法
公开(公告)号：US07870357B2
公开(公告)日：2011-01-11
申请号：US12242870
申请日：2008-09-30
申请人： Paul G. Davis , Frederick A. Ware , Craig E. Hampel
发明人： Paul G. Davis , Frederick A. Ware , Craig E. Hampel
IPC分类号： G06F12/00
CPC分类号： G11C7/1039 , G06F13/1626 , G11C7/1006 , G11C7/22 , G11C11/4076 , G11C2207/2218 , G11C2207/229
摘要： A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked.
摘要翻译：一种操作包括存储器核心的存储器组件的方法，包括从外部控制线接收指定写入操作的写入命令。写命令在接收到写命令后第一个时间段被存储。在第一时间段之后，响应写入命令启动写入操作。在写入操作期间，接收数据的未屏蔽部分被写入存储器核心，其中数据的未屏蔽部分是由接收到的掩码信息识别为不被掩蔽的数据的位。

98. 发明授权

US07813178B2 Semiconductor memory device and write control method therefor 有权
标题翻译：半导体存储器件及其写控制方法
公开(公告)号：US07813178B2
公开(公告)日：2010-10-12
申请号：US12003163
申请日：2007-12-20
申请人： Kiyoshi Nakai
发明人： Kiyoshi Nakai
IPC分类号： G11C11/34
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/1096 , G11C8/06 , G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C13/0069 , G11C2013/0076 , G11C2207/2218 , G11C2207/2245
摘要： Disclosed is a semiconductor memory device which includes a read data latch that holds read data from a phase change memory and latches write data entered from outside and holds write data entered from outside, a write data latch that holds the write data for a cell for the time duration of a preset number of cycles until start of data write, a transfer switch that controls whether or not an output of the read data latch is to be transferred to the write data latch, a comparator circuit that decides whether or not data transferred to the write data latch via the transfer switch and held in the write data latch and data in the read data latch are coincident with each other, and a write flag latch that latches an output of the comparator circuit. Data is written only in case there is a write request and the result of comparison of the comparator circuit indicates non-coincidence, that is, only in bits in need of data writing.
摘要翻译：公开了一种半导体存储器件，其包括读取数据锁存器，其保存来自相变存储器的读取数据并锁存从外部输入的写入数据，并保存从外部输入的写入数据;写入数据锁存器，直到数据写入开始为止的预设数量的周期的持续时间;控制读取数据锁存器的输出是否被传送到写数据锁存器的转移开关;判定数据传送到通过转换开关写入数据锁存器并保持在写入数据锁存器中，读取数据锁存器中的数据彼此一致，并且写入标志锁存器锁存比较器电路的输出。只有在存在写请求的情况下才写入数据，并且比较电路的比较结果表示不一致，即仅在需要数据写入的位中。

99. 发明授权

US07496709B2 Integrated circuit memory device having delayed write timing based on read response time 有权
标题翻译：具有基于读取响应时间的延迟写入定时的集成电路存储器件
公开(公告)号：US07496709B2
公开(公告)日：2009-02-24
申请号：US11953803
申请日：2007-12-10
申请人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
发明人： Richard M. Barth , Frederick A. Ware , Donald C. Stark , Craig E. Hampel , Paul G. Davis , Abhijit M. Abhyankar , James A. Gasbarro , David Nguyen
IPC分类号： G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.
摘要翻译：集成电路存储器件包括用于存储写入数据的存储器核心，用于接收写入数据的第一组互连资源以及用于接收与写入数据相关联的写入命令的第二组互连资源。指示掩码信息是否包括在写入命令中的信息，其中当包括在写入命令中时，掩码信息指定是否选择性地将写入数据的部分写入存储器核心。

100. 发明申请

US20090010092A1 ADDRESS COUNTER, SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME, AND DATA PROCESSING SYSTEM 失效
标题翻译：地址计数器，具有该存储器的半导体存储器件和数据处理系统
公开(公告)号：US20090010092A1
公开(公告)日：2009-01-08
申请号：US12167719
申请日：2008-07-03
申请人： Hiroki FUJISAWA
发明人： Hiroki FUJISAWA
IPC分类号： G11C8/00
CPC分类号： G11C8/04 , G11C7/1018 , G11C11/4076 , G11C19/00 , G11C21/00 , G11C2207/2218
摘要： An address counter includes FIFO units and first and second command counters that control the groups. The first command counter has a first mode in which any one of input gates is conducted in response to a first internal command and a second mode in which a plurality of input gates are conducted in response to an internal command. The second command counter has a first mode in which any one of output gates is conducted in response to one of second and third internal commands and second mode in which corresponding output gates are each conducted in response to one of the second and third internal commands. Thereby, when tCCD is small, the first mode can be selected, and when the tCCD is large, the second mode can be selected.
摘要翻译：地址计数器包括FIFO单元和控制组的第一和第二命令计数器。第一命令计数器具有第一模式，其中响应于第一内部命令进行输入门中的任一个并且响应于内部命令进行多个输入门的第二模式。第二命令计数器具有第一模式，其中响应于第二和第三内部命令之一进行输出门中的任一个，并且响应于第二和第三内部命令中的一个而相应地输出相应的输出门的第二模式。因此，当tCCD小时，可以选择第一模式，并且当tCCD大时，可以选择第二模式。

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