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91. 发明授权

US09021238B2 System for accessing a register file using an address retrieved from the register file 有权
标题翻译：使用从寄存器文件检索的地址访问寄存器文件的系统
公开(公告)号：US09021238B2
公开(公告)日：2015-04-28
申请号：US13372103
申请日：2012-02-13
申请人： Xiao Tao Chang , Qiang Liu
发明人： Xiao Tao Chang , Qiang Liu
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , G06F9/35 , G06F9/30 , G06F9/38
CPC分类号： G06F9/35 , G06F9/30098 , G06F9/382
摘要： A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a register in a register file are used as an index, and then, the register file pointed to by said index is accessed based on said index; an execution stage where an access result of said decode stage is received, and computations are implemented according to the access result of the decode stage.
摘要翻译：公开了一种数据处理系统和方法。该系统包括指令获取阶段，其中获取指令并将特定指令输入到解码级; 解码阶段，其中所述特定指令指示寄存器文件中的寄存器的内容被用作索引，然后基于所述索引访问由所述索引指向的寄存器文件; 其中接收到所述解码级的访问结果的执行阶段，并且根据解码级的访问结果实现计算。

92. 发明申请

US20150106593A1 INSTRUCTION AND LOGIC FOR PROCESSING TEXT STRINGS 审中-公开
公开(公告)号：US20150106593A1
公开(公告)日：2015-04-16
申请号：US14576136
申请日：2014-12-18
申请人： Intel Corporation
发明人： Michael A. Julier , Jeffrey D. Gray , Srinivas Chennupaty , Sean P. Mirkes , Mark P. Seconi
IPC分类号： G06F9/30 , G06F12/08
CPC分类号： G06F9/30145 , G06F7/06 , G06F9/30 , G06F9/3001 , G06F9/30021 , G06F9/30029 , G06F9/30036 , G06F9/30098 , G06F9/30109 , G06F9/3013 , G06F9/30167 , G06F9/3017 , G06F9/30185 , G06F9/30192 , G06F9/34 , G06F9/3802 , G06F9/3824 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F12/0875 , G06F2212/452
摘要： Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store a result of a comparison between each data element of a first and second operand corresponding to a first and second text string, respectively.

93. 发明申请

US20150089200A1 ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS 审中-公开
公开(公告)号：US20150089200A1
公开(公告)日：2015-03-26
申请号：US14562223
申请日：2014-12-05
申请人： Intel Corporation
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30094 , G06F9/30098
摘要： A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

94. 发明申请

US20150089199A1 ROTATE INSTRUCTIONS THAT COMPLETE EXECUTION EITHER WITHOUT WRITING OR READING FLAGS 审中-公开
公开(公告)号：US20150089199A1
公开(公告)日：2015-03-26
申请号：US14562145
申请日：2014-12-05
申请人： Intel Corporation
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30094 , G06F9/30098
摘要： A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

95. 发明申请

US20150074354A1 DEVICE, SYSTEM AND METHOD FOR USING A MASK REGISTER TO TRACK PROGRESS OF GATHERING ELEMENTS FROM MEMORY 审中-公开
标题翻译：使用掩码寄存器跟踪记忆元素进度的设备，系统和方法
公开(公告)号：US20150074354A1
公开(公告)日：2015-03-12
申请号：US14541458
申请日：2014-11-14
申请人： Intel Corporation
发明人： Eric Sprangle , Anwar Rohillah , Robert Cavin , Andrew T. Forsyth , Michael Abrash
IPC分类号： G06F12/08 , G06F9/30
CPC分类号： G06F15/8069 , G06F9/30043 , G06F9/30047 , G06F9/30098 , G06F9/30101 , G06F9/345 , G06F9/383 , G06F12/02 , G06F12/0875 , G06F2212/452 , G06F2212/602 , G06F2212/6028
摘要： A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.
摘要翻译：一种用于将值分配给第一寄存器中的元件的装置，系统和方法，其中第一寄存器中的每个数据字段对应于要写入第二寄存器的数据元素，并且对于第一寄存器中的每个数据字段，值可以指示相应的数据元素尚未被写入第二寄存器，第二值指示对应的数据元素已被写入第二寄存器，读取第一寄存器中每个数据域的值，并且为第一寄存器中的每个数据字段具有第一值，收集对应的数据元素并将相应的数据元素写入第二寄存器，并将第一寄存器中的数据字段的值从第一值改变为第二值。描述和要求保护其他实施例。

96. 发明申请

US20150049106A1 QUEUING SYSTEM FOR REGISTER FILE ACCESS 有权
标题翻译：用于注册文件访问的排队系统
公开(公告)号：US20150049106A1
公开(公告)日：2015-02-19
申请号：US13970578
申请日：2013-08-19
申请人： Apple Inc.
发明人： Andrew M. Havlir , Sreevathsa Ramachandra , William V. Miller
IPC分类号： G06T1/60
CPC分类号： G06T1/20 , G06F9/30098 , G06F9/30105 , G06F9/3012 , G06F9/30123 , G06F9/3824 , G06F9/3885
摘要： Techniques are disclosed relating to arbitration of requests to access a register file. In one embodiment, an apparatus includes a write queue and a register file that includes multiple entries. In one embodiment, the apparatus is configured to select a request from a plurality of requests based on a plurality of request characteristics, and write data from the accepted request into a write queue. In one embodiment, the request characteristics include: whether a request is a last request from an agent for a given register file entry and whether the request finishes a previous request. In one embodiment, a final arbiter is configured to select among requests from the write queue, a read queue, and multiple execution pipelines to access banks of the register file in a given cycle.
摘要翻译：公开了关于访问寄存器文件的请求的仲裁的技术。在一个实施例中，装置包括写入队列和包括多个条目的寄存器文件。在一个实施例中，设备被配置为基于多个请求特性从多个请求中选择请求，并将数据从接受的请求写入写入队列。在一个实施例中，请求特征包括：请求是否是针对给定寄存器文件条目的代理的最后请求以及请求是否完成先前的请求。在一个实施例中，最终仲裁器被配置为在给定周期中从写入队列，读取队列和多个执行管线的请求中选择访问寄存器文件的存储体。

97. 发明申请

US20150046686A1 METHOD FOR EXECUTING BLOCKS OF INSTRUCTIONS USING A MICROPROCESSOR ARCHITECTURE HAVING A REGISTER VIEW, SOURCE VIEW, INSTRUCTION VIEW, AND A PLURALITY OF REGISTER TEMPLATES 审中-公开
标题翻译：使用具有注册视图的微处理器架构，源视图，指令视图和多个寄存器模板来执行指令块的方法
公开(公告)号：US20150046686A1
公开(公告)日：2015-02-12
申请号：US14212533
申请日：2014-03-14
申请人： Soft Machines, Inc.
发明人： Mohammad A. Abdallah
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/3009 , G06F9/3836 , G06F9/3838 , G06F9/3853 , G06F9/3857 , G06F9/3863 , G06F9/5005
摘要： A method for executing blocks of instructions using a microprocessor architecture having a register view, source view, instruction view, and a plurality of register templates. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions; using a register view data structure, wherein the register view data structure stores destinations corresponding to the instruction blocks; using a source view data structure, wherein the source view data structure stores sources corresponding to the instruction blocks; and using an instruction view data structure, wherein the instruction view data structure stores instructions corresponding to the instruction blocks.
摘要翻译：一种使用具有寄存器视图，源视图，指令视图和多个寄存器模板的微处理器架构来执行指令块的方法。该方法包括使用全局前端接收输入指令序列; 将指令分组以形成指令块; 使用多个寄存器模板来通过用对应于指令块的块号填充寄存器模板来跟踪指令目的地和指令源，其中对应于指令块的块号指示指令块之间的相互依赖关系; 使用注册视图数据结构，其中所述注册视图数据结构存储与所述指令块相对应的目的地; 使用源视图数据结构，其中所述源视图数据结构存储与所述指令块相对应的源; 并且使用指令视图数据结构，其中指令视图数据结构存储与指令块相对应的指令。

98. 发明申请

US20150046683A1 METHOD FOR USING REGISTER TEMPLATES TO TRACK INTERDEPENDENCIES AMONG BLOCKS OF INSTRUCTIONS 审中-公开
标题翻译：使用寄存器模板跟踪说明书块中的联系的方法
公开(公告)号：US20150046683A1
公开(公告)日：2015-02-12
申请号：US14212203
申请日：2014-03-14
申请人： Soft Machines, Inc.
发明人： Mohammad A. Abdallah
IPC分类号： G06F9/30 , G06F9/50
CPC分类号： G06F9/30098 , G06F9/3009 , G06F9/3836 , G06F9/3838 , G06F9/3853 , G06F9/3857 , G06F9/3863 , G06F9/5005
摘要： A method for executing instructions using register templates to track interdependencies among blocks of instructions. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; and using a register template to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions.
摘要翻译：一种用于使用寄存器模板执行指令以跟踪指令块之间的相互依赖性的方法。该方法包括使用全局前端接收输入指令序列; 将指令分组以形成指令块; 以及使用寄存器模板通过用对应于指令块的块号填充寄存器模板来跟踪指令目的地和指令源，其中对应于指令块的块号表示指令块之间的相互依赖性。

99. 发明申请

US20150026435A1 INSTRUCTION SET ARCHITECTURE WITH EXTENSIBLE REGISTER ADDRESSING 有权
标题翻译：具有可扩展寄存器寻址的指令集架构
公开(公告)号：US20150026435A1
公开(公告)日：2015-01-22
申请号：US13947734
申请日：2013-07-22
申请人： International Business Machines Corporation
发明人： Adam J. Muff , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/30098 , G06F9/30138 , G06F9/3016
摘要： A method and circuit arrangement selectively source and/or write data from/to extended registers of an extended register file based in part on whether an operand address of an instruction references a primary register of primary register file configured to store a pointer to the extended register. Control logic connected to the primary register file and the extended register file determines whether the operand address references a primary register configured to store a pointer, and responsive to the determination, the control logic causes execution logic to selectively source and/or write data from/to the extended register pointed to by the pointer stored in the referenced primary register.
摘要翻译：一种方法和电路装置部分地基于指令的操作数地址是否引用主寄存器文件的主寄存器来选择性地从扩展寄存器文件的/扩展寄存器写入和/或写入数据，该主寄存器文件被配置为存储指向扩展寄存器的指针。连接到主寄存器文件和扩展寄存器文件的控制逻辑确定操作数地址是否引用被配置为存储指针的主寄存器，并且响应于该确定，控制逻辑使执行逻辑选择性地从/ 到存储在引用的主寄存器中的指针指向的扩展寄存器。

100. 发明申请

US20150019840A1 Highly Integrated Scalable, Flexible DSP Megamodule Architecture 有权
标题翻译：高度集成的可扩展，灵活的DSP Megamodule架构
公开(公告)号：US20150019840A1
公开(公告)日：2015-01-15
申请号：US14331986
申请日：2014-07-15
申请人： Texas Instruments Incorporated
发明人： Timothy D. Anderson , Joseph Zbiciak , Duc Quang Bui , Abnijeet A. Chachad , Kai Chirca , Naveen Bhoria , Matthew D. Pierson , Daniel Wu
IPC分类号： G06F9/30 , G06F9/345
CPC分类号： G06F9/3016 , G06F9/30014 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/30145 , G06F9/32 , G06F9/345 , G06F9/3802 , G06F9/3822 , G06F9/383 , G06F9/3867 , G06F11/00 , G06F11/10 , G06F11/1048 , G06F12/0875 , G06F12/0897 , G06F2212/452 , G06F2212/60
摘要： This invention addresses implements a range of interesting technologies into a single block. Each DSP CPU has a streaming engine. The streaming engines include: a SE to L2 interface that can request 512 bits/cycle from L2; a loose binding between SE and L2 interface, to allow a single stream to peak at 1024 bits/cycle; one-way coherence where the SE sees all earlier writes cached in system, but not writes that occur after stream opens; full protection against single-bit data errors within its internal storage via single-bit parity with semi-automatic restart on parity error.
摘要翻译：本发明解决了将一系列有趣的技术实现到单个块中。每个DSP CPU都有一个流式引擎。流式引擎包括：可以从L2请求512位/周期的SE到L2接口; SE和L2接口之间的松散绑定，允许单个流以1024位/周期达到峰值; 单向一致性，其中SE看到所有较早的写入缓存在系统中，而不是在流打开之后发生的写入; 通过单位奇偶校验，通过奇偶校验错误半自动重新启动，完全保护其内部存储器内的单位数据错误。

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