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1. 发明申请

US20150269118A1 Apparatus and Method for Processing an Instruction Matrix Specifying Parallel and Dependent Operations 有权
公开(公告)号：US20150269118A1
公开(公告)日：2015-09-24
申请号：US14733827
申请日：2015-06-08
申请人： Soft Machines, Inc.
发明人： Mohammad A. Abdallah
IPC分类号： G06F15/80 , G06F9/38 , G06F9/30
CPC分类号： G06F15/8007 , G06F7/483 , G06F7/5318 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30109 , G06F9/3012 , G06F9/30123 , G06F9/30141 , G06F9/3016 , G06F9/30181 , G06F9/30189 , G06F9/3824 , G06F9/3828 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , G06F15/80
摘要： A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions.

2. 发明申请

US20140281416A1 METHOD FOR IMPLEMENTING A REDUCED SIZE REGISTER VIEW DATA STRUCTURE IN A MICROPROCESSOR 有权
标题翻译：在微处理器中实现减小尺寸寄存器视图数据结构的方法
公开(公告)号：US20140281416A1
公开(公告)日：2014-09-18
申请号：US14214176
申请日：2014-03-14
申请人： Soft Machines, Inc.
发明人： Mohammad A. Abdallah
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3802 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/3857 , G06F9/3863
摘要： A method for implementing a reduced size register view data structure in a microprocessor. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of multiplexers to access ports of a scheduling array to store the instruction blocks as a series of chunks.
摘要翻译：一种用于在微处理器中实现缩小尺寸寄存器观看数据结构的方法。该方法包括使用全局前端接收输入指令序列; 将指令分组以形成指令块; 使用多个多路复用器访问调度阵列的端口以将指令块存储为一系列块。

3. 发明申请

US20130091340A1 Apparatus and Method for Processing an Instruction Matrix Specifying Parallel and Dependent Operations 有权
公开(公告)号：US20130091340A1
公开(公告)日：2013-04-11
申请号：US13691609
申请日：2012-11-30
申请人： Soft Machines, Inc.
发明人： Mohammad A. Abdallah
IPC分类号： G06F15/80
CPC分类号： G06F15/8007 , G06F7/483 , G06F7/5318 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30109 , G06F9/3012 , G06F9/30123 , G06F9/30141 , G06F9/3016 , G06F9/30181 , G06F9/30189 , G06F9/3824 , G06F9/3828 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , G06F15/80
摘要： A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions.

4. 发明授权

US09436476B2 Method and apparatus for sorting elements in hardware structures 有权
标题翻译：用于在硬件结构中排列元素的方法和装置
公开(公告)号：US09436476B2
公开(公告)日：2016-09-06
申请号：US14052571
申请日：2013-10-11
申请人： Soft Machines, Inc.
发明人： Mohammad A. Abdallah , Mandeep Singh
IPC分类号： G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/3855 , G06F9/3834 , G06F9/3857
摘要： A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.
摘要翻译：公开了一种在硬件结构中对元件进行排序的方法。该方法包括从预定范围内的无序输入队列（UIQ）中选择多个元素以响应于找到预定范围的至少一个最高有效位与相关标识符的相应位的匹配，多个元素。该方法还包括将多个元件中的每一个呈现给相应的多路复用器。此外，所述方法包括：响应于找到与所述多个元素中的每一个相关联的相应标识符的至少一个最低有效位与所述有序队列的端口号之间的匹配来产生用于使能多路复用器的选择信号。最后，该方法包括将与所选择的元素标识符相关联的分组从所启用的多路复用器转发到有序队列的匹配端口号。

5. 发明授权

US09501280B2 Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer 有权
标题翻译：高速缓存存储数据，通过地址计算加载指令获取，标签用作消费指令的相关联名称
公开(公告)号：US09501280B2
公开(公告)日：2016-11-22
申请号：US14194589
申请日：2014-02-28
申请人： Soft Machines, Inc.
发明人： Mohammad A. Abdallah
IPC分类号： G06F9/34 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48
CPC分类号： G06F9/30123 , G06F9/30043 , G06F9/3009 , G06F9/30134 , G06F9/30138 , G06F9/3016 , G06F9/34 , G06F9/342 , G06F9/3808 , G06F9/3824 , G06F9/3826 , G06F9/383 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3853 , G06F9/3857 , G06F9/3885 , G06F9/3891 , G06F9/462 , G06F9/4843
摘要： A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instruction formats includes a virtual register file, register cache and register file hierarchy. A self-generating and synchronizing dynamic and static threading architecture provides efficient context switching.
摘要翻译：用于复杂指令格式的动态生成，执行，同步和并行化的统一架构包括虚拟寄存器文件，寄存器高速缓存和寄存器文件层次结构。自生产和同步动态和静态线程架构提供了有效的上下文切换。

6. 发明申请

US20150046686A1 METHOD FOR EXECUTING BLOCKS OF INSTRUCTIONS USING A MICROPROCESSOR ARCHITECTURE HAVING A REGISTER VIEW, SOURCE VIEW, INSTRUCTION VIEW, AND A PLURALITY OF REGISTER TEMPLATES 审中-公开
标题翻译：使用具有注册视图的微处理器架构，源视图，指令视图和多个寄存器模板来执行指令块的方法
公开(公告)号：US20150046686A1
公开(公告)日：2015-02-12
申请号：US14212533
申请日：2014-03-14
申请人： Soft Machines, Inc.
发明人： Mohammad A. Abdallah
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/3009 , G06F9/3836 , G06F9/3838 , G06F9/3853 , G06F9/3857 , G06F9/3863 , G06F9/5005
摘要： A method for executing blocks of instructions using a microprocessor architecture having a register view, source view, instruction view, and a plurality of register templates. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions; using a register view data structure, wherein the register view data structure stores destinations corresponding to the instruction blocks; using a source view data structure, wherein the source view data structure stores sources corresponding to the instruction blocks; and using an instruction view data structure, wherein the instruction view data structure stores instructions corresponding to the instruction blocks.
摘要翻译：一种使用具有寄存器视图，源视图，指令视图和多个寄存器模板的微处理器架构来执行指令块的方法。该方法包括使用全局前端接收输入指令序列; 将指令分组以形成指令块; 使用多个寄存器模板来通过用对应于指令块的块号填充寄存器模板来跟踪指令目的地和指令源，其中对应于指令块的块号指示指令块之间的相互依赖关系; 使用注册视图数据结构，其中所述注册视图数据结构存储与所述指令块相对应的目的地; 使用源视图数据结构，其中所述源视图数据结构存储与所述指令块相对应的源; 并且使用指令视图数据结构，其中指令视图数据结构存储与指令块相对应的指令。

7. 发明申请

US20150046683A1 METHOD FOR USING REGISTER TEMPLATES TO TRACK INTERDEPENDENCIES AMONG BLOCKS OF INSTRUCTIONS 审中-公开
标题翻译：使用寄存器模板跟踪说明书块中的联系的方法
公开(公告)号：US20150046683A1
公开(公告)日：2015-02-12
申请号：US14212203
申请日：2014-03-14
申请人： Soft Machines, Inc.
发明人： Mohammad A. Abdallah
IPC分类号： G06F9/30 , G06F9/50
CPC分类号： G06F9/30098 , G06F9/3009 , G06F9/3836 , G06F9/3838 , G06F9/3853 , G06F9/3857 , G06F9/3863 , G06F9/5005
摘要： A method for executing instructions using register templates to track interdependencies among blocks of instructions. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; and using a register template to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions.
摘要翻译：一种用于使用寄存器模板执行指令以跟踪指令块之间的相互依赖性的方法。该方法包括使用全局前端接收输入指令序列; 将指令分组以形成指令块; 以及使用寄存器模板通过用对应于指令块的块号填充寄存器模板来跟踪指令目的地和指令源，其中对应于指令块的块号表示指令块之间的相互依赖性。

8. 发明申请

US20140181475A1 Parallel Processing of a Sequential Program Using Hardware Generated Threads and Their Instruction Groups Executing on Plural Execution Units and Accessing Register File Segments Using Dependency Inheritance Vectors Across Multiple Engines 有权
标题翻译：使用硬件生成的线程及其指令组对多个执行单元执行的顺序程序的并行处理和使用多个引擎的依赖继承向量访问寄存器文件段
公开(公告)号：US20140181475A1
公开(公告)日：2014-06-26
申请号：US14194589
申请日：2014-02-28
申请人： Soft Machines, Inc.
发明人： Mohammad A. Abdallah
IPC分类号： G06F9/38
CPC分类号： G06F9/30123 , G06F9/30043 , G06F9/3009 , G06F9/30134 , G06F9/30138 , G06F9/3016 , G06F9/34 , G06F9/342 , G06F9/3808 , G06F9/3824 , G06F9/3826 , G06F9/383 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3853 , G06F9/3857 , G06F9/3885 , G06F9/3891 , G06F9/462 , G06F9/4843
摘要： A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instruction formats includes a virtual register file, register cache and register file hierarchy. A self-generating and synchronizing dynamic and static threading architecture provides efficient context switching.
摘要翻译：用于复杂指令格式的动态生成，执行，同步和并行化的统一架构包括虚拟寄存器文件，寄存器高速缓存和寄存器文件层次结构。自生产和同步动态和静态线程架构提供了有效的上下文切换。

9. 发明授权

US09053292B2 Processor executing super instruction matrix with register file configurable for single or multiple threads operations 有权
标题翻译：执行超级指令矩阵的处理器可以配置为单线程或多线程操作的寄存器文件
公开(公告)号：US09053292B2
公开(公告)日：2015-06-09
申请号：US13691609
申请日：2012-11-30
申请人： Soft Machines, Inc.
发明人： Mohammad A. Abdallah
IPC分类号： G06F9/38 , G06F15/80 , G06F7/533 , G06F9/30 , G06F7/483 , G06F7/53 , G06F7/544
CPC分类号： G06F15/8007 , G06F7/483 , G06F7/5318 , G06F7/5338 , G06F7/5443 , G06F9/3001 , G06F9/30109 , G06F9/3012 , G06F9/30123 , G06F9/30141 , G06F9/3016 , G06F9/30181 , G06F9/30189 , G06F9/3824 , G06F9/3828 , G06F9/3838 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F9/3887 , G06F9/3889 , G06F9/3891 , G06F15/80
摘要： A processor has a register file configurable for different execution modes. In one mode the multiple register segments form a single register file where each register segment stores a Multiple Instructions Multiple Data (MIMD) super instruction matrix issuing four simultaneous instruction matrices where each individual instruction within each of the four simultaneous instruction matrices is a scalar or Single Instruction Multiple Data (SIMD). Another execution mode has the multiple register segments forming individual independent register tiles with individual register state to support simultaneous processing of separate threads, where each instruction matrix is associated with a separate thread and a separate register file segment. Another execution mode has the multiple register segments forming a single thread register file, where register segments are duplicated in multiple segments of the register file to store the results of simultaneously executed non-dependent instruction matrices that are dynamically issued from a single thread instruction sequence.
摘要翻译：处理器具有可配置用于不同执行模式的寄存器文件。在一种模式中，多个寄存器段形成单个寄存器文件，其中每个寄存器段存储发出四个同时指令矩阵的多指令多数据（MIMD）超指令矩阵，其中四个同时指令矩阵中的每一个中的每个单独指令是标量或单个指令多重数据（SIMD）。另一种执行模式具有多个寄存器段，其形成具有单独寄存器状态的独立寄存器块，以支持单独线程的同时处理，其中每个指令矩阵与单独的线程和单独的寄存器文件段相关联。另一执行模式具有形成单个线程寄存器文件的多个寄存器段，其中寄存器段在寄存器堆栈的多个段中复制以存储从单个线程指令序列动态发出的同时执行的非依赖指令矩阵的结果。

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