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91. 发明授权

US4941083A Method and apparatus for initiating interlock read transactions on a multiprocessor computer system 失效
标题翻译：用于在多处理器计算机系统上启动联锁读取事务的方法和装置
公开(公告)号：US4941083A
公开(公告)日：1990-07-10
申请号：US44486
申请日：1987-05-01
申请人： Richard B. Gillett, Jr. , Douglas D. Williams
发明人： Richard B. Gillett, Jr. , Douglas D. Williams
IPC分类号： G06F15/16 , G06F9/46 , G06F9/52 , G06F13/366 , G06F13/42 , G06F15/177
CPC分类号： G06F9/466 , G06F13/4217
摘要： A processor node providing exclusive read-modify-write operations in a computer system having multiple processors interconnected by a pended bus and employing multiple lock bits. The processor generates an interlock read command which is transmitted as a transfer over the pended bus to a memory or I/O mode. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the command transfer. The command transfer, including an interlock read command, is stored in an input queue in memory and is processed in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue. The memory obtains access to the pended bus through an arbitration process and transmits a response message including the contents of the memory location specified in the interlock read command at an unspecified time after initiation of the interlock read command. A subsequent interlock read command from the processor to the same memory location will result in a denial of access to the specified location and in the generation of a second type of response message by the memory which indicates that the specified location is locked.
摘要翻译：处理器节点在具有多个处理器的计算机系统中提供排他性的读 - 修改 - 写入操作，所述多个处理器通过挂起总线互连并采用多个锁定位。处理器产生互锁读取命令，该命令作为通过挂起总线的传输被传送到存储器或I / O模式。在命令传输的每个总线周期之后，确认确认将由存储器发送回处理器两个总线周期。包括联锁读取命令的命令传输存储在存储器中的输入队列中，并被存储器依次处理。对指定的存储器位置的第一联锁读取命令导致为该位置设置锁定位，以及包括要由存储器生成并存储在输出队列中的指定位置的内容的第一类型的响应消息。存储器通过仲裁处理获得对待处理总线的访问，并且在启动互锁读取命令之后的未指定时间发送包括在联锁读取命令中指定的存储器位置的内容的响应消息。从处理器到相同存储器位置的随后的互锁读取命令将导致拒绝对指定位置的访问以及存储器生成指示指定位置被锁定的第二类型的响应消息。

92. 发明授权

US4845522A Data communication system for camera system 失效
标题翻译：相机系统数据通信系统
公开(公告)号：US4845522A
公开(公告)日：1989-07-04
申请号：US112280
申请日：1987-10-26
申请人： Hiroyuki Kataoka
发明人： Hiroyuki Kataoka
IPC分类号： G03B17/14 , G06F13/42
CPC分类号： G06F13/4217 , G03B17/14
摘要： A data communication system in which data communication between a camera and an accessory such as a strobe is performed by transmitting items of data in sequence in synchronism with clock pulses. If the data communication is not performed normally, the system detects an error in this communication, and the operation of performing data communication using these items of data is recommenced.
摘要翻译：一种数据通信系统，其中通过与时钟脉冲同步地顺序发送数据项目来执行摄像机和诸如选通信号的附件之间的数据通信。如果数据通信不正常，则系统检测到该通信中的错误，并且重新开始使用这些数据项进行数据通信的操作。

93. 发明授权

US4787064A Circuit module with interface circuits for connecting to plurality of busses operating in different operating modes 失效
标题翻译：具有用于连接到以不同操作模式操作的多个总线的接口电路的电路模块
公开(公告)号：US4787064A
公开(公告)日：1988-11-22
申请号：US928704
申请日：1986-11-10
申请人： Wolfgang Wagner
发明人： Wolfgang Wagner
IPC分类号： H04L25/02 , G06F13/36 , G06F13/38 , G06F13/42 , G06F15/00
CPC分类号： G06F13/4217 , G06F13/385
摘要： Circuit module assembly, includes a circuit module, integrated circuits with a first set of operating characteristics disposed on the module, a bus having a second set of operating characteristics, contact elements connected to the bus for transmitting data, address and control signals. Switchable interface circuits disposed on the module and connected to the integrated circuits are to the contact elements for matching the signals to be transmitted through the contact elements to one of the sets of characteristics.
摘要翻译：电路模块组件包括电路模块，具有设置在模块上的第一组工作特性的集成电路，具有第二组工作特性的总线，连接到总线的用于传输数据，地址和控制信号的接触元件。设置在模块上并连接到集成电路的可切换接口电路是接触元件，用于将要通过接触元件传输的信号与特征集合中的一个相匹配。

94. 发明授权

US4611276A Device for superimposition of the successive stages of the transfer of data among several data processing units 失效
标题翻译：用于在多个数据处理单元之间叠加数据传送的连续阶段的装置
公开(公告)号：US4611276A
公开(公告)日：1986-09-09
申请号：US591237
申请日：1984-03-20
申请人： Daniel R. Vinot
发明人： Daniel R. Vinot
IPC分类号： G06F9/46 , G06F13/362 , G06F13/378 , G06F13/42 , G06F15/16 , G06F15/177 , G06F13/36
CPC分类号： G06F13/378 , G06F13/4217
摘要： A control logic circuit (C) is provided in each unit such as processors andemories in a multiple processor data processing system. Each control logic circuit (C) is equipped with a priority circuit (P12) which at one input receives the eligible local calls (RQ.sub.i L) of the unit itself and at the other input receives external calls (RQ.sub.k) transmitted by the other units. The control logic circuit (C) enables control by its unit of a transmission but only when its priority circuit (P12) recognizes that unit as having the highest priority among the other units. The logic circuit (C) together with a T circuit (13) selects local calls as a function of the state of occupation of the data lines of the transmission bus.

95. 发明授权

US4604743A Bus structure for an image processor 失效
标题翻译：图像处理器的总线结构
公开(公告)号：US4604743A
公开(公告)日：1986-08-05
申请号：US673960
申请日：1984-11-21
申请人： Radu Alexandru
发明人： Radu Alexandru
IPC分类号： G06F13/36 , G06F13/37 , G06F13/42 , G06T1/20 , H04L12/40 , H04L12/403 , H04N7/00 , H04J3/02 , H04J3/16 , H04J3/24
CPC分类号： G06F13/4217 , G06F13/37 , G06T1/20
摘要： A bus structure for an image processing system connecting a plurality of devices capable of transmitting and receiving packets of N data words serially on N sub-buses wherein the data sub-buses are spatially multiplexed and an address bus is time multiplexed.
摘要翻译：一种图像处理系统的总线结构，其连接多个能够在N个子总线上串行发送和接收N个数据字的分组的装置，其中数据子总线被空间复用并且地址总线被时分复用。

96. 发明授权

US4564899A I/O Channel bus 失效
标题翻译： I / O通道总线
公开(公告)号：US4564899A
公开(公告)日：1986-01-14
申请号：US426045
申请日：1982-09-28
申请人： Kenneth Holly , Gehrard J. Smith
发明人： Kenneth Holly , Gehrard J. Smith
IPC分类号： G06F13/26 , G06F13/28 , G06F13/362 , G06F13/42 , G06F3/00
CPC分类号： G06F13/4217 , G06F13/26 , G06F13/28 , G06F13/362
摘要： A data bus system utilizing logical transfer channels provides high data rates (even over long distances) and good error detection. The basic function of a transfer channel is to enable temporary assignment of some portion of the bus resource to a specific device and then to allow simple, quick addressing of that device by reference to that channel. There are a relatively small number of transfer channels (say four) that may be attached or detached by the channel processor (IOCP) to meet the data flow requirements. For a transfer to occur between the IOCP (15) and a device (30a, 30b), the IOCP (15) first effects an "attach" operation to assign the device (30a, 30b) a transfer channel for the duration of the transfer. Thereafter, the IOCP (15) allocates the bus cycles among the currently attached transfer channels according to any desired priority scheme, subject to the constraint that the device on a transfer channel be ready to send or receive data before that transfer channel may be granted cycles.
摘要翻译：使用逻辑传输通道的数据总线系统提供高数据速率（甚至长距离）和良好的错误检测。传输信道的基本功能是使总线资源的一部分临时分配给特定设备，然后通过参考该信道来允许简单，快速地寻址该设备。通道处理器（IOCP）可能连接或分离的传输通道（例如四个）数量相对较少，以满足数据流要求。为了在IOCP（15）和设备（30a，30b）之间发生转移，IOCP（15）首先进行“附着”操作，以在传送期间分配设备（30a，30b）传输信道。此后，IOCP（15）根据任何期望的优先权方案在当前附加的传输信道之间分配总线周期，受限于传输信道上的设备准备好在该传输信道被授予周期之前发送或接收数据。

97. 发明授权

US4231084A Data transfer system 失效
标题翻译：数据传输系统
公开(公告)号：US4231084A
公开(公告)日：1980-10-28
申请号：US858820
申请日：1977-12-08
申请人： Masaaki Yoshizaki , Kenichi Mizuno
发明人： Masaaki Yoshizaki , Kenichi Mizuno
IPC分类号： G06F13/10 , G06F9/30 , G06F13/12 , G06F13/42 , G06F3/04
CPC分类号： G06F13/122 , G06F13/4217
摘要： There is provided a data transfer system for use in a data processing system. The data processing system comprises a central processor for processing information in accordance with an instruction stored in a main memory equipment, a peripheral equipment operable by receiving the instruction from the central processor and transmitting to the central processor a control information which requires the central processor to effect successive controlling operation, and an address bus, data bus and execution bus connecting the central processor to the peripheral equipment. When transferring data from the central processor to the peripheral equipment, the operating sequence procedure of the central processor is changed in accordance with the content on the status bus through which the control information from the peripheral equipment is transmitted to the central processor, whereby a sequence commensurate with the status of the peripheral equipment in operation is effected within the same instruction.
摘要翻译：提供了一种用于数据处理系统的数据传输系统。该数据处理系统包括一个中央处理器，用于根据存储在主存储器设备中的指令来处理信息，外围设备可通过从中央处理器接收指令并向中央处理器传送控制信息，该控制信息需要中央处理器连续控制操作，以及将中央处理器连接到外围设备的地址总线，数据总线和执行总线。当将数据从中央处理器传送到外围设备时，中央处理器的操作顺序过程根据状态总线上的内容而改变，通过该内容来自外围设备的控制信息被传送到中央处理器，与正在运行的外围设备的状态相称，在相同的指令中进行。

98. 发明授权

US3870825A Time-division multiplex communication system 失效
标题翻译：时分多址通信系统
公开(公告)号：US3870825A
公开(公告)日：1975-03-11
申请号：US32139473
申请日：1973-01-05
申请人： ENGINEERED DEVICES COMPANY
发明人： ROBERTS ROBERT C , ALCORN EDWARD B
IPC分类号： G06F13/42 , G09B5/12 , H04J3/08
CPC分类号： G09B5/12 , G06F13/4217
摘要： A time-division multiplex system including multiple transmitters and receivers; a master clock cyclically generating once per clock frame a series of different clock numbers in the form of differing sequences of binary signals, each clock number constituting a different time slot; a clock highway interconnecting the transmitters and receivers and to which the clock number signals are applied; a comparison network at each transmitter and receiver which sequentially compares the clock number signals on the clock highway with a number at the transmitter and receiver for the purpose of selecting the time slot during which each transmitter and receiver operates to transmit and receive audio information, respectively, over an audio information highway which also interconnects the transmitters and receivers.
摘要翻译：一种包括多个发射机和接收机的时分复用系统; 主时钟以每个时钟帧周期性地产生一系列不同的二进制信号序列的不同时钟数，每个时钟数构成不同的时隙; 互连发射机和接收机并且应用时钟编号信号的时钟高速公路; 在每个发射机和接收机处的比较网络，其顺序地将时钟高速公路上的时钟数信号与发射机和接收机处的号码进行比较，以分别选择每个发射机和接收机分别在其间发送和接收音频信息的时隙在通过发送器和接收器互连的音频信息高速公路上。

99. 发明申请

US20190121754A1 DYNAMIC BUS INVERSION WITH PROGRAMMABLE TERMINATION LEVEL TO MAINTAIN PROGRAMMABLE TARGET RATIO OF ONES AND ZEROS IN SIGNAL LINES 审中-公开
公开(公告)号：US20190121754A1
公开(公告)日：2019-04-25
申请号：US16028137
申请日：2018-07-05
申请人： Intel Corporation
发明人： Christopher P. MOZAK , James A. McCALL , Bryan K. CASPER
IPC分类号： G06F13/16 , G06F13/40 , G06F13/42
CPC分类号： G06F13/1657 , G06F11/10 , G06F13/4004 , G06F13/4022 , G06F13/4072 , G06F13/4217 , G06F13/4221 , G06F13/4234 , H04L25/4915 , Y02D10/14 , Y02D10/151
摘要： Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (“noninverted signal”) and a number and/or ratio of ones and zeros in an inverted version of the signal (“inverted signal”). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

100. 发明申请

US20180046384A1 Portable Lighting Device with Reconfigurable User Interface 审中-公开
公开(公告)号：US20180046384A1
公开(公告)日：2018-02-15
申请号：US15671971
申请日：2017-08-08
申请人： Mag Instrument, Inc.
发明人： Stacey West
IPC分类号： G06F3/06 , G06F13/16 , G06F13/42
CPC分类号： G06F3/0611 , F21L4/00 , F21V23/0428 , G06F3/0655 , G06F3/0679 , G06F13/1689 , G06F13/4217 , G06F13/4243 , H05B33/0845 , H05B33/0854 , H05B37/0209 , Y02B20/40 , Y02D10/14 , Y02D10/151
摘要： A portable lighting device that provides different user interfaces that may be selected by the user. Each user interface may provide one or more operational modes, such as on mode, power save mode, strobe mode or momentary mode. After a user interface is selected, the user may select on of the operational modes. The portable lighting device may be a flashlight.

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