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91. 发明申请

US20120265917A1 DATA TRANSFERRING DEVICE 审中-公开
标题翻译：数据传输设备
公开(公告)号：US20120265917A1
公开(公告)日：2012-10-18
申请号：US13465277
申请日：2012-05-07
申请人： Praveen Raghavan , Miguel Glassee
发明人： Praveen Raghavan , Miguel Glassee
IPC分类号： G06F13/28
CPC分类号： G06F13/405 , Y02D10/14 , Y02D10/151
摘要： A data transfer device for transferring data on a platform, in particular for transferring simultaneous data between different components of the platform, is disclosed. In one aspect, the data transfer device is adapted for simultaneous transfer of data between at least 3 ports of which at least one is an input port and at least one is an output port. The data transfer device has at least two controllers for executing instructions that transfer data between an input port and an output port. The controllers are adapted for receiving a synchronization instruction for synchronizing between the controllers and/or a synchronization instruction for synchronizing input ports and output ports.
摘要翻译：公开了一种用于在平台上传送数据，特别是用于在平台的不同部件之间传送同时数据的数据传送装置。在一个方面，数据传输设备适于在至少3个端口之间同时传输数据，其中至少一个端口是输入端口，并且至少一个端口是输出端口。数据传输装置具有至少两个用于执行在输入端口和输出端口之间传送数据的指令的控制器。控制器适于接收用于在控制器之间同步的同步指令和/或用于同步输入端口和输出端口的同步指令。

92. 发明申请

US20120179852A1 ONE-WAY BUS BRIDGE 审中-公开
标题翻译：单程总线桥
公开(公告)号：US20120179852A1
公开(公告)日：2012-07-12
申请号：US13229640
申请日：2011-09-09
申请人： Gerald R. McEvoy
发明人： Gerald R. McEvoy
IPC分类号： G06F13/16 , G06F13/36
CPC分类号： G06F13/4286 , G06F13/1673 , G06F13/4027 , G06F13/405 , H04L63/0209 , H04L63/0227
摘要： A one-way bus bridge pair that transfers secure data in one direction, the bus bridge pair including a transmitting bus bridge, a receiving bus bridge, and a link. The link can connect the transmitting bus bridge and receiving bus bridge. The transmitting bus bridge may be arranged not to receive any data from the receiving bus bridge, and the receiving bus bridge may be arranged not to send any data to the transmitting bus bridge.
摘要翻译：一个单向总线桥对，用于在一个方向上传输安全数据，总线桥对包括发送总线桥，接收总线桥和链路。该链路可以连接发射总线桥和接收总线桥。发射总线桥可以被布置为不从接收总线桥接器接收任何数据，并且接收总线桥可以被布置为不向发射总线桥发送任何数据。

93. 发明申请

US20120131374A1 JITTER REDUCTION METHOD AND APPARATUS FOR DISTRIBUTED SYNCHRONISED CLOCK ARCHITECTURE 有权
标题翻译：用于分布式同步时钟结构的抖动减少方法和装置
公开(公告)号：US20120131374A1
公开(公告)日：2012-05-24
申请号：US13321707
申请日：2010-05-20
申请人： Peter Graham Foster , Alex Kouznetsov
发明人： Peter Graham Foster , Alex Kouznetsov
IPC分类号： G06F1/12
CPC分类号： G06F13/423 , G06F1/08 , G06F1/12 , G06F11/3027 , G06F13/10 , G06F13/4022 , G06F13/4027 , G06F13/405 , G06F13/4282 , G06F2213/0042 , H04L7/04 , H04L7/08
摘要： A method of reducing jitter in a local clock of a synchronised USB device attached to a USB Hub, the USB Hub having a local clock and repeater circuitry, comprising: observing a USB data stream with the USB Hub, the data stream having a data stream bit rate; the USB Hub decoding a periodic signal structure in the USB data stream; the USB Hub generating an event signal in response to decoding of the periodic signal structure; and the USB Hub locking a frequency of the local clock of the USB Hub to the periodic event signal. The local clock of the USB Hub is adapted to be a clocking source for the repeater circuitry of the USB Hub at substantially an integer multiple of a frequency of the data stream bit rate.
摘要翻译：一种减少连接到USB集线器的同步USB设备的本地时钟中的抖动的方法，所述USB集线器具有本地时钟和中继器电路，包括：利用所述USB集线器观察USB数据流，所述数据流具有数据流比特率 USB集线器解码USB数据流中的周期性信号结构; 所述USB集线器响应于所述周期性信号结构的解码而产生事件信号; 并且USB集线器将USB集线器的本地时钟的频率锁定到周期性事件信号。 USB集线器的本地时钟适合作为数据流比特率频率的大致整数倍的USB集线器的中继器电路的时钟源。

94. 发明申请

US20120059965A1 PRECISION SYNCHRONISATION ARCHITECTURE FOR SUPERSPEED UNIVERSAL SERIAL BUS DEVICES 失效
标题翻译：超级通用串行总线设备精密同步架构
公开(公告)号：US20120059965A1
公开(公告)日：2012-03-08
申请号：US13320401
申请日：2010-05-20
申请人： Peter Graham Foster
发明人： Peter Graham Foster
IPC分类号： G06F13/14
CPC分类号： G06F13/423 , G06F1/08 , G06F1/12 , G06F11/3027 , G06F13/10 , G06F13/4022 , G06F13/4027 , G06F13/405 , G06F13/4282 , G06F2213/0042 , H04L7/04 , H04L7/08
摘要： A method of providing a synchronisation channel to a SuperSpeed USB device is provided. The method including a SuperSpeed communication channel connection to the SuperSpeed USB device with a USB cable that has USB 2.0 D+ and D− data signalling lines disabled or disconnected at an upstream connection point; multiplexing synchronization information onto the D+/D− data signalling lines at the upstream connection point; and demultiplexing the synchronization information from the D+/D− signalling lines at a downstream connection point of the cable; whereby the synchronisation channel is maintained across the D+/D− data signalling lines.
摘要翻译：提供了一种向SuperSpeed USB设备提供同步信道的方法。该方法包括使用USB电缆连接到SuperSpeed USB设备的SuperSpeed通信通道，该USB电缆在上游连接点处禁用或断开USB 2.0 D +和D-数据信号线; 将同步信息复用到上游连接点的D + / D-数据信号线上; 以及在电缆的下游连接点处从D + / D-信令线解复用同步信息; 由此在D + / D-数据信号线路上维持同步信道。

95. 发明授权

US07657689B1 Methods and apparatus for handling reset events in a bus bridge 失效
标题翻译：用于处理总线桥中的复位事件的方法和装置
公开(公告)号：US07657689B1
公开(公告)日：2010-02-02
申请号：US10681860
申请日：2003-10-07
申请人： Andrew Crosland , Andrew Draper
发明人： Andrew Crosland , Andrew Draper
IPC分类号： G06F13/36 , G06F13/00 , H03L7/00
CPC分类号： G06F13/405
摘要： Methods and apparatus are provided for handling reset events in a bus bridge. A system on a programmable chip includes master components and slave components supporting various bus protocols. Bus bridges allow components using different bus protocols to interact. Reset of a distinct subset of programmable chip components or the synchronization of reset signals across disparate clock domains is allowed by effectively handling reset related signals at a bus bridge.
摘要翻译：提供了用于处理总线桥中的复位事件的方法和装置。可编程芯片上的系统包括支持各种总线协议的主组件和从组件。总线桥允许使用不同总线协议的组件进行交互。通过有效地处理总线桥上的复位相关信号，可以允许在不同的时钟域上复位可编程芯片组件的不同子集或复位信号的同步。

96. 发明授权

US07543172B2 Strobe masking in a signaling system having multiple clock domains 有权
标题翻译：具有多个时钟域的信令系统中的频闪屏蔽
公开(公告)号：US07543172B2
公开(公告)日：2009-06-02
申请号：US11019432
申请日：2004-12-21
申请人： Jade M. Kizer , Sivakumar Doraiswamy , Benedict Lau
发明人： Jade M. Kizer , Sivakumar Doraiswamy , Benedict Lau
IPC分类号： G06F1/12
CPC分类号： G11C11/4076 , G06F13/1689 , G06F13/405 , G11C7/222 , G11C8/18 , G11C11/4063 , G11C11/4072 , G11C11/4096
摘要： Systems and methods for masking strobe signals in strobe-based systems are provided below. These strobe-masking systems receive a strobe signal from a component operating under one clock domain and in turn generate a masked version of the strobe signal. Components of a host system use the masked strobe signal to receive or transfer data from the clock domain of the strobe signal through a mesochronous clock domain crossing into a different clock domain.
摘要翻译：以下提供了用于屏蔽基于选通信号的系统中的选通信号的系统和方法。这些选通屏蔽系统从在一个时钟域下操作的组件接收选通信号，并且产生选通信号的屏蔽版本。主机系统的组件使用屏蔽的选通信号通过穿过不同时钟域的中间时钟域从选通信号的时钟域接收或传输数据。

97. 发明授权

US07486718B2 Architectures, circuits, systems and methods for reducing latency in data communications 有权
标题翻译：用于减少数据通信延迟的架构，电路，系统和方法
公开(公告)号：US07486718B2
公开(公告)日：2009-02-03
申请号：US10634218
申请日：2003-08-04
申请人： Pantas Sutardja , Lei Wu , Hongying Sheng
发明人： Pantas Sutardja , Lei Wu , Hongying Sheng
IPC分类号： H03K11/00 , H04L25/60 , H04L25/64
CPC分类号： G06F13/405
摘要： Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal. The systems generally relate to those that include the present architecture and/or circuit. The method generally includes determining a phase difference between first and second periodic signals, one of the periodic signals being recovered from a data stream; adjusting the other periodic signal in response to the phase difference and filtered information from the recovered periodic signal; and transmitting the data stream in accordance with said adjusted periodic signal. The present invention advantageously eliminates a FIFO memory in the data path, thereby reducing transceiver latency and improving system performance.
摘要翻译：用于促进数据通信和/或减少数据通信中的延迟的电路，架构，系统和方法。该架构包括时钟恢复环路，其接收来自主机设备的数据并提供恢复的时钟信号，滤波器电路接收恢复的时钟信号信息，并提供响应于恢复的时钟信号信息和两个时钟信号调整发射机时钟的控制信号以及接收控制信号并根据发射机时钟向目的地设备发送数据的发射机。电路通常包括时钟对准块，其接收第一和第二周期信号并响应于此提供控制信号，用于第一周期性信号信息的滤波器以及被配置为组合控制信号和滤波信息的逻辑电路，由此提供调整信号用于第二周期信号。系统通常涉及包括本架构和/或电路的系统。该方法通常包括确定第一和第二周期信号之间的相位差，从数据流中恢复一个周期信号; 响应于来自恢复的周期信号的相位差和滤波信息调整另一周期信号; 以及根据所述调整的周期信号发送数据流。本发明有利地消除数据路径中的FIFO存储器，从而减少收发机等待时间并提高系统性能。

98. 发明申请

US20080263228A1 Single-chip microcomputer 审中-公开
标题翻译：单片机
公开(公告)号：US20080263228A1
公开(公告)日：2008-10-23
申请号：US12151390
申请日：2008-05-05
申请人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
发明人： Shumpei Kawasaki , Yasushi Akao , Kouki Noguchi , Atsushi Hasegawa , Hiroshi Ohsuga , Keiichi Kurakazu , Kiyoshi Matsubara , Akio Hayakawa , Yoshitaka Ito
IPC分类号： G06F3/00
CPC分类号： G06F9/3001 , G06F12/0893 , G06F13/36 , G06F13/405 , G06F15/7817 , H04W28/08 , H04W52/0216 , H04W88/02 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D70/142 , Y02D70/26
摘要： A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.
摘要翻译：一种单片微计算机，包括：具有中央处理单元和与其连接的高速缓冲存储器的第一总线; 具有动态存储器访问控制电路和与其连接的外部总线接口的第二总线; 用于选择性地连接第一总线和第二总线的断开控制器; 第三总线，其具有与其连接的周边模块，并且具有比第一和第二总线的总线周期更低的总线周期; 以及用于进行数据传送和第二总线与第三总线之间的同步的总线状态控制器。单片机具有三条分开的内部总线，以减少信号传输路径上的负载能力，从而可以高速实现信号传输。此外，隔离所需要的没有操作速度的外围模块，从而可以降低功耗。

99. 发明申请

US20080189453A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：半导体集成电路器件及其工作方法
公开(公告)号：US20080189453A1
公开(公告)日：2008-08-07
申请号：US11941169
申请日：2007-11-16
申请人： Joo Hyung MUN
发明人： Joo Hyung MUN
IPC分类号： G06F13/12 , G06F3/00 , G06F13/20
CPC分类号： G06F13/405
摘要： A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a central processing unit (CPU) configured to output first control signals in response to a first clock signal, a first bus connected to the CPU, a bridge circuit connected to the first bus, a second bus connected to the bridge circuit, a plurality of peripheral circuits connected to the second bus, and a clock monitor connected to the first bus or the second bus and configured to output a register value corresponding to a second clock signal to the bridge circuit. The bridge circuit receives the first control signals, generates second control signals based on the register value, and outputs the second control signals to one of the peripheral circuits via the second bus.
摘要翻译：提供了一种半导体集成电路器件。半导体集成电路装置包括：中央处理单元（CPU），被配置为响应于第一时钟信号输出第一控制信号，连接到CPU的第一总线，连接到第一总线的桥接电路，连接到第一总线的第二总线桥接电路，连接到第二总线的多个外围电路以及连接到第一总线或第二总线的时钟监视器，并且被配置为将对应于第二时钟信号的寄存器值输出到桥接电路。桥接电路接收第一控制信号，基于寄存器值产生第二控制信号，并经由第二总线将第二控制信号输出到外围电路之一。

100. 发明授权

US07334073B2 Method of and apparatus for interfacing buses operating at different speeds 有权
标题翻译：用于以不同速度操作的总线的接口的方法和装置
公开(公告)号：US07334073B2
公开(公告)日：2008-02-19
申请号：US11142463
申请日：2005-06-02
申请人： Sang-ik Choi , Shin-wook Kang , Hyang-suk Park
发明人： Sang-ik Choi , Shin-wook Kang , Hyang-suk Park
IPC分类号： G06F13/36
CPC分类号： G06F13/405 , Y02D10/14 , Y02D10/151
摘要： The present invention relates to a bridge for interfacing buses within an embedded system. There is provided a method of interfacing a first bus and a second bus operating at different speeds, the method includes counting a match value assigned to a predetermined peripheral device among peripheral devices connected to the second bus for each cycle of a clock signal received from the first bus, and keeping a read state or a write state for the predetermined peripheral device by continuously outputting a read signal or a write signal for the predetermined peripheral device to the second bus, during the counting of the match value. According to the present invention, it is not necessary to operate depending on a peripheral device operating at the lowest speed among peripheral devices, and not necessary to add wrappers to the peripheral devices, by employing the AHB-to-ISA bridge variably adjusting the output times of output signals to an ISA bus.
摘要翻译：本发明涉及一种用于在嵌入式系统内接口总线的桥接器。提供了一种接口第一总线和以不同速度工作的第二总线的方法，该方法包括对从第二总线连接到第二总线的外围设备分配给与从第二总线接收的时钟信号的每个周期相匹配的匹配值进行计数并且在匹配值的计数期间，通过连续地向第二总线输出用于预定的外围设备的读取信号或写入信号，为预定的外围设备保持读取状态或写入状态。根据本发明，不需要根据外围设备中以最低速度操作的外围设备进行操作，并且不需要通过使用可变地调整输出的AHB-ISA桥接器向外围设备添加封装输出信号到ISA总线的次数。

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