专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080189453A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：半导体集成电路器件及其工作方法
公开(公告)号：US20080189453A1
公开(公告)日：2008-08-07
申请号：US11941169
申请日：2007-11-16
申请人： Joo Hyung MUN
发明人： Joo Hyung MUN
IPC分类号： G06F13/12 , G06F3/00 , G06F13/20
CPC分类号： G06F13/405
摘要： A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a central processing unit (CPU) configured to output first control signals in response to a first clock signal, a first bus connected to the CPU, a bridge circuit connected to the first bus, a second bus connected to the bridge circuit, a plurality of peripheral circuits connected to the second bus, and a clock monitor connected to the first bus or the second bus and configured to output a register value corresponding to a second clock signal to the bridge circuit. The bridge circuit receives the first control signals, generates second control signals based on the register value, and outputs the second control signals to one of the peripheral circuits via the second bus.
摘要翻译：提供了一种半导体集成电路器件。半导体集成电路装置包括：中央处理单元（CPU），被配置为响应于第一时钟信号输出第一控制信号，连接到CPU的第一总线，连接到第一总线的桥接电路，连接到第一总线的第二总线桥接电路，连接到第二总线的多个外围电路以及连接到第一总线或第二总线的时钟监视器，并且被配置为将对应于第二时钟信号的寄存器值输出到桥接电路。桥接电路接收第一控制信号，基于寄存器值产生第二控制信号，并经由第二总线将第二控制信号输出到外围电路之一。

2. 发明授权

US06714466B2 System of performing a repair analysis for a semiconductor memory device having a redundant architecture 有权
标题翻译：对具有冗余架构的半导体存储器件执行修复分析的系统
公开(公告)号：US06714466B2
公开(公告)日：2004-03-30
申请号：US10080710
申请日：2002-02-25
申请人： Sang Wook Park , Joo Hyung Mun , Hyeok Man Kwon
发明人： Sang Wook Park , Joo Hyung Mun , Hyeok Man Kwon
IPC分类号： G11C700
CPC分类号： G11C29/72 , G11C29/44
摘要： Two temporary buffers are employed alternatively storing a fail address data designated from a test operation, in which one of the temporary buffers transfers the fail address data to a data buffer in order to perform a repair analysis while the other one is storing the fail address data. Accordingly, the test and repair analysis operations are simultaneously performed. The capability of the rearrangement that includes the movement and exchange between the column and row fail address data enhances redundancy efficiency and yields of the memory device.
摘要翻译：采用两个临时缓冲器，其中存储从测试操作指定的故障地址数据，其中一个临时缓冲器将故障地址数据传送到数据缓冲器，以执行修复分析，而另一个存储故障地址数据。因此，同时执行测试和修复分析操作。包括列和行失败地址数据之间的移动和交换的重新布置的能力提高了存储器件的冗余效率和产量。

3. 发明授权

US07953999B2 Semiconductor integrated circuit device and method of operating the same 有权
标题翻译：半导体集成电路器件及其操作方法
公开(公告)号：US07953999B2
公开(公告)日：2011-05-31
申请号：US11941169
申请日：2007-11-16
申请人： Joo Hyung Mun
发明人： Joo Hyung Mun
IPC分类号： G06F1/00 , G06F1/04 , G06F13/36
CPC分类号： G06F13/405
摘要： A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a central processing unit (CPU) configured to output first control signals in response to a first clock signal, a first bus connected to the CPU, a bridge circuit connected to the first bus, a second bus connected to the bridge circuit, a plurality of peripheral circuits connected to the second bus, and a clock monitor connected to the first bus or the second bus and configured to output a register value corresponding to a second clock signal to the bridge circuit. The bridge circuit receives the first control signals, generates second control signals based on the register value, and outputs the second control signals to one of the peripheral circuits via the second bus.
摘要翻译：提供了一种半导体集成电路器件。半导体集成电路装置包括：中央处理单元（CPU），被配置为响应于第一时钟信号输出第一控制信号，连接到CPU的第一总线，连接到第一总线的桥接电路，连接到第一总线的第二总线桥接电路，连接到第二总线的多个外围电路以及连接到第一总线或第二总线的时钟监视器，并且被配置为将对应于第二时钟信号的寄存器值输出到桥接电路。桥接电路接收第一控制信号，基于寄存器值产生第二控制信号，并经由第二总线将第二控制信号输出到外围电路之一。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式