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91. 发明授权

US06936881B2 Capacitor that includes high permittivity capacitor dielectric 有权
公开(公告)号：US06936881B2
公开(公告)日：2005-08-30
申请号：US10628020
申请日：2003-07-25
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： H01G4/228 , H01L21/00 , H01L21/02 , H01L21/334 , H01L21/762 , H01L21/8239 , H01L21/84 , H01L27/00 , H01L27/105 , H01L27/108 , H01L27/12 , H01L29/92 , H01L29/94
CPC分类号： H01L27/0805 , H01L21/84 , H01L27/1203 , H01L28/55 , H01L28/65 , H01L29/66181 , H01L29/94 , Y10S257/905 , Y10S257/908
摘要： A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

92. 发明申请

US20050121706A1 Semiconductor nano-rod devices 审中-公开
公开(公告)号：US20050121706A1
公开(公告)日：2005-06-09
申请号：US11031703
申请日：2005-01-07
申请人： Hao-Yu Chen , Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
发明人： Hao-Yu Chen , Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336 , H01L29/423 , H01L29/775 , H01L29/786 , H01L21/00 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/76 , H01L29/94 , H01L31/0392 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7854 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/66742 , H01L29/66795 , H01L29/775
摘要： In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.

93. 发明授权

US06872606B2 Semiconductor device with raised segment 有权
标题翻译：具有凸起部分的半导体器件
公开(公告)号：US06872606B2
公开(公告)日：2005-03-29
申请号：US10406403
申请日：2003-04-03
申请人： Hao-Yu Chen , Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
发明人： Hao-Yu Chen , Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/00 , H01L21/336 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/786 , H01L31/062
CPC分类号： H01L29/78618 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/78684
摘要： A device having a raised segment, and a manufacturing method for same. An SOI wafer is provided having a substrate, an insulating layer disposed over the substrate, and a layer of semiconductor material disposed over the insulating layer. The semiconductor material is patterned to form a mesa structure. The wafer is annealed to form a raised segment on the mesa structure.
摘要翻译：具有凸起部分的装置及其制造方法。提供SOI晶片，其具有衬底，设置在衬底上的绝缘层和设置在绝缘层上的半导体材料层。图案化半导体材料以形成台面结构。将晶片退火以在台面结构上形成凸起的段。

94. 发明授权

US06864519B2 CMOS SRAM cell configured using multiple-gate transistors 有权
标题翻译：使用多栅极晶体管配置的CMOS SRAM单元
公开(公告)号：US06864519B2
公开(公告)日：2005-03-08
申请号：US10305728
申请日：2002-11-26
申请人： Yee-Chia Yeo , Chenming Hu , Fu-Liang Yang
发明人： Yee-Chia Yeo , Chenming Hu , Fu-Liang Yang
IPC分类号： H01L21/336 , H01L21/8239 , H01L21/8242 , H01L21/8244 , H01L27/10 , H01L27/11 , H01L27/12 , H01L29/423 , H01L29/786
CPC分类号： H01L27/1104 , H01L27/11 , H01L27/1211 , H01L29/42384 , H01L29/66795 , H01L29/785
摘要： A complementary metal-oxide-semiconductor static random access memory cell that is formed by a pair of P-channel multiple-gate field-effect transistors (P-MGFETs), a pair of N-channel multiple-gate field-effect transistors (N-MGFETs), a second pair of N-MGFETs that has a drain respectively connected to a connection linking the respective drain of the N-MGFET of the first pair of N-MGFET to the drain of the P-MGFET of the pair of P-MGFETs; a pair of complementary bit lines, each respectively connected to the source of the N-MGFET of the second pair of N-MGFETS; and a word line connected to the gates of the N-MGFETs of the second pair of N-MGFETs.
摘要翻译：由一对P沟道多栅极场效应晶体管（P-MGFET），一对N沟道多栅极场效应晶体管（N）构成的互补金属氧化物半导体静态随机存取存储单元 -MGFET），第二对N-MGFET，其漏极分别连接到将第一对N-MGFET的N-MGFET的相应漏极连接到该对P-MGFET的漏极的连接 -MGFETs 一对互补位线，分别连接到第二对N-MGFETS的N-MGFET的源极; 以及连接到第二对N-MGFET的N-MGFET的门的字线。

95. 发明申请

US20050040493A1 Resistor with reduced leakage 有权
标题翻译：电阻泄漏减少
公开(公告)号：US20050040493A1
公开(公告)日：2005-02-24
申请号：US10667871
申请日：2003-09-22
申请人： Yee-Chia Yeo , Chenming Hu
发明人： Yee-Chia Yeo , Chenming Hu
IPC分类号： H01L21/02 , H01L23/60 , H01L27/12 , H01L21/20
CPC分类号： H01L27/1203 , H01L28/20
摘要： A resistor 100 is formed in a semiconductor layer 106, e.g., a silicon layer on an SOI substrate. A body region 108 is formed in a portion of the semiconductor layer 106 and is doped to a first conductivity type (e.g., n-type or p-type). A first contact region 110, which is also doped to the first conductivity type, is formed in the semiconductor layer 106 adjacent the body region 108. A second contact region 112 is also formed in the semiconductor layer 106 and is spaced from the first contact region 110 by the body region 108. A dielectric layer 116 overlies the body region and is formed from a material with a relative permittivity greater than about 8. An electrode 114 overlies the dielectric 116.
摘要翻译：电阻器100形成在半导体层106中，例如SOI衬底上的硅层。体区108形成在半导体层106的一部分中并被掺杂到第一导电类型（例如，n型或p型）。第一接触区域110也被掺杂到第一导电类型，形成在邻近主体区域108的半导体层106中。第二接触区域112也形成在半导体层106中并且与第一接触区域电介质层116覆盖在主体区域上，并且由相对介电常数大于约8的材料形成。电极114覆盖电介质116。

96. 发明申请

US20050035410A1 Semiconductor diode with reduced leakage 审中-公开
标题翻译：半导体二极管漏电流减少
公开(公告)号：US20050035410A1
公开(公告)日：2005-02-17
申请号：US10641813
申请日：2003-08-15
申请人： Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/84 , H01L27/06 , H01L27/08 , H01L27/12 , H01L29/49 , H01L29/739 , H01L29/76 , H01L21/8238
CPC分类号： H01L29/4983 , H01L21/84 , H01L27/0629 , H01L27/0814 , H01L27/1203 , H01L29/7392
摘要： A diode 100 is formed on a silicon-on-insulator substrate that includes a silicon layer overlying an insulator layer 142. An active region is formed in the silicon layer and includes a p-doped region 108 and an n-doped region 106 separated by a body region 110. A high permittivity gate dielectric 114 overlies the body region 110 and a gate electrode 112 overlies the gate dielectric 114. As an example, the diode can be used for ESD protection.
摘要翻译：二极管100形成在绝缘体上硅衬底上，其包括覆盖绝缘体层142的硅层。有源区形成在硅层中，并且包括p掺杂区108和n掺杂区106，主体区域110.高电容率栅极电介质114覆盖在主体区域110上，并且栅电极112覆盖在栅极电介质114上。作为示例，二极管可以用于ESD保护。

97. 发明授权

US06855606B2 Semiconductor nano-rod devices 有权
标题翻译：半导体纳米棒器件
公开(公告)号：US06855606B2
公开(公告)日：2005-02-15
申请号：US10370792
申请日：2003-02-20
申请人： Hao-Yu Chen , Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
发明人： Hao-Yu Chen , Yee-Chia Yeo , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336 , H01L29/423 , H01L29/775 , H01L29/786 , H01L29/76 , H01L21/4763 , H01L27/12 , H01L29/784
CPC分类号： H01L29/7854 , B82Y10/00 , H01L29/0673 , H01L29/42384 , H01L29/42392 , H01L29/66742 , H01L29/66795 , H01L29/775
摘要： In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.
摘要翻译：在制造半导体器件的方法中，半导体层被图案化以在半导体层中形成源极区，沟道区和漏极区。沟道区域在源极区域和漏极区域之间延伸。通道区域的角部通过对通道区域进行退火以形成纳米棒结构而变圆。然后将纳米棒结构的一部分用作栅极通道。优选地，栅极电介质和栅极电极都围绕纳米杆结构缠绕，栅极电介质位于纳米棒结构和栅电极之间，以形成晶体管器件。

98. 发明授权

US06812116B2 Method of fabricating a wafer with strained channel layers for increased electron and hole mobility for improving device performance 有权
标题翻译：制造具有应变通道层的晶片以提高电子和空穴迁移率以提高器件性能的方法
公开(公告)号：US06812116B2
公开(公告)日：2004-11-02
申请号：US10318454
申请日：2002-12-13
申请人： Chien-Chao Huang , Yee-Chia Yeo , Kuo-Nan Yang , Chun-Chieh Lin , Chenming Hu
发明人： Chien-Chao Huang , Yee-Chia Yeo , Kuo-Nan Yang , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L21301
CPC分类号： H01L21/3247 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02658 , H01L21/02664 , H01L21/324 , H01L21/76259 , H01L29/1054
摘要： A method for making a SOI wafer with a strained silicon layer for increased electron and hole mobility is achieved. The method forms a porous silicon layer on a seed wafer. A H2 anneal is used to form a smooth surface on the porous silicon. A strain free (relaxed) epitaxial SixGe1−x layer is deposited and a bonding layer is formed. The seed wafer is then bonded to a handle wafer having an insulator on the surface. A spray etch is used to etch the porous Si layer resulting in a SOI handle wafer having portions of the porous Si layer on the relaxed SixGe1−x. The handle wafer is then annealed in H2 to convert the porous Si to a smooth strained Si layer on the relaxed SiGe layer of the SOI wafer.
摘要翻译：实现了制造具有用于增加电子和空穴迁移率的应变硅层的SOI晶片的方法。该方法在种子晶片上形成多孔硅层。使用H2退火在多孔硅上形成光滑表面。沉积无应变的（松弛的）外延六面体Ge-x层并形成结合层。然后将种子晶片结合到在表面上具有绝缘体的手柄晶片。使用喷涂蚀刻来蚀刻多孔Si层，导致SOI处理晶片，其具有在松弛的SixGe1-x上的多孔Si层的部分。然后将处理晶片在H 2中退火以将多孔Si转化为SOI晶片的松弛SiGe层上的平滑应变Si层。

99. 发明授权

US09673280B2 Cobalt silicidation process for substrates comprised with a silicon-germanium layer 有权
公开(公告)号：US09673280B2
公开(公告)日：2017-06-06
申请号：US11714416
申请日：2007-03-06
申请人： Chien-Chao Huang , Yee-Chia Yeo , Chao-Hsiung Wang , Chun-Chieh Lin , Chenming Hu
发明人： Chien-Chao Huang , Yee-Chia Yeo , Chao-Hsiung Wang , Chun-Chieh Lin , Chenming Hu
IPC分类号： H01L29/10 , H01L21/265 , H01L21/28 , H01L21/285 , H01L21/8238 , H01L29/66 , H01L29/78 , H01L21/02
CPC分类号： H01L29/1054 , H01L21/02142 , H01L21/265 , H01L21/28052 , H01L21/28518 , H01L21/28525 , H01L21/823807 , H01L21/823814 , H01L29/66636 , H01L29/7834
摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

100. 发明授权

US08488102B2 Immersion fluid for immersion lithography, and method of performing immersion lithography 有权
标题翻译：浸没式光刻用浸渍液，以及进行浸渍光刻的方法
公开(公告)号：US08488102B2
公开(公告)日：2013-07-16
申请号：US12731752
申请日：2010-03-25
申请人： Yee-Chia Yeo , Burn-Jeng Lin , Chenming Hu
发明人： Yee-Chia Yeo , Burn-Jeng Lin , Chenming Hu
IPC分类号： G03F7/207
CPC分类号： G03F7/70341
摘要： An immersion lithographic system 10 comprises an optical surface 51, an immersion fluid 60 with a pH less than 7 contacting at least a portion of the optical surface, and a semiconductor structure 80 having a topmost photoresist layer 70 wherein a portion of the photoresist is in contact with the immersion fluid. Further, a method for illuminating a semiconductor structure 80 having a topmost photoresist layer 70 comprising the steps of: introducing an immersion fluid 60 into a space between an optical surface 51 and the photoresist layer wherein the immersion fluid has a pH of less than 7, and directing light preferably with a wavelength of less than 450 nm through the immersion fluid and onto the photoresist.
摘要翻译：浸没式光刻系统10包括光学表面51，具有与光学表面的至少一部分接触的pH小于7的浸没流体60以及具有最高光致抗蚀剂层70的半导体结构80，其中光致抗蚀剂的一部分在与浸液接触。此外，一种用于照射具有最高光致抗蚀剂层70的半导体结构80的方法，包括以下步骤：将浸没流体60引入到光学表面51和光致抗蚀剂层之间的空间中，其中浸没流体的pH小于7，并且通过浸渍流体优选将波长小于450nm的光引导到光致抗蚀剂上。

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