专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US06269430B1 Method for controlling a process of writing data sent by a central processing unit to a memory by using a central processing unit interface 有权
标题翻译：用于通过使用中央处理单元接口来控制将由中央处理单元发送的数据写入存储器的处理的方法
公开(公告)号：US06269430B1
公开(公告)日：2001-07-31
申请号：US09342711
申请日：1999-06-29
申请人： Chia-Hsin Chen , You-Ming Chiu , Jiin Lai
发明人： Chia-Hsin Chen , You-Ming Chiu , Jiin Lai
IPC分类号： G06F1200
CPC分类号： G06F12/0875 , G06F13/4243 , G06F2212/303
摘要： A method for a CPU interface to control a writing process that writes data sent from a CPU to a memory. The CPU interface controls the writing process through steps mainly including receiving a write request and data from a CPU, sending a dummy request to the memory control circuit of the memory circuit, and then writing the data to a memory of the memory circuit. After the CPU interface receives a write request from the CPU, the CPU interface sends a dummy request to the memory control circuit to pre-charge and activate the designative memory page of the memory circuit before the data is sent to the memory circuit. Since the designative memory page is always pre-charged and activated while the data is received at the memory control circuit, the memory control circuit sends only a write command to the memory for writing the data to the memory without further pre-charging and activating the designative memory page. Therefore, the total number of clock cycles required for processing a write request is shortened.
摘要翻译：一种CPU接口的方法，用于控制将从CPU发送到存储器的数据写入的写入过程。 CPU接口通过主要包括从CPU接收写入请求和数据，向存储器电路的存储器控制电路发送伪请求，然后将数据写入存储器电路的存储器的步骤来控制写入过程。在CPU接口从CPU接收到写请求之后，CPU接口向存储器控制电路发送伪请求，以在数据被发送到存储器电路之前对存储器电路的指定存储器页进行预充电和激活。由于在存储器控制电路中接收到数据时，指定存储器页面总是被预先充电并被激活，所以存储器控制电路仅将写入命令发送到存储器，用于将数据写入存储器，而无需进一步的预充电和激活指定记忆页面。因此，缩短了处理写请求所需的总时钟周期数。

92. 发明授权

US06202167B1 Computer chip set for computer mother board referencing various clock rates 失效
标题翻译：计算机芯片组用于计算机主板，参考各种时钟频率
公开(公告)号：US06202167B1
公开(公告)日：2001-03-13
申请号：US09099977
申请日：1998-06-19
申请人： Jiin Lai , Heng-Chen Ho , Kuo-Ping Liu
发明人： Jiin Lai , Heng-Chen Ho , Kuo-Ping Liu
IPC分类号： G06F108
CPC分类号： G06F1/08
摘要： A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other clock rate. The first and second clock rates are in virtual synchronism and have a fixed ratio between them. The computer chip set utilizes a phase signal generator capable of generating a set of phase signals and a signal conversion logic circuit for generating the output signal referencing one of the first and second clock rates other than the one referenced by the input signal. This computer chip set can allow the computer mother board to be operated without waiting a state so that the data processing efficiency of the computer mother board can be enhanced. A multiplexer means used in the computer chip set of the invention has an output which is selectively multiplexed between the first clock rate and the second clock rate to serve as a third clock signal. This computer chip set allows the designer to use a slower clock rate to drive the DRAM.
摘要翻译：计算机芯片组被设计为在具有至少两个时钟速率的计算机母板上使用，包括第一时钟速率和第二时钟速率，用于将参考第一或第二时钟速率的输入信号转换为参考的输出信号另一个时钟速率。第一和第二时钟速率是虚拟同步的，并且它们之间具有固定的比例。计算机芯片组利用能够产生一组相位信号的相位信号发生器和信号转换逻辑电路，用于产生参考第一和第二时钟速率之一的输出信号，而不是由输入信号所参考的那个。该计算机芯片组可以允许计算机母板在不等待状态的情况下操作，从而可以提高计算机母板的数据处理效率。在本发明的计算机芯片组中使用的多路复用器装置具有在第一时钟速率和第二时钟速率之间选择性地多路复用以用作第三时钟信号的输出。该计算机芯片组允许设计者使用较慢的时钟速率来驱动DRAM。

93. 发明授权

US06079027A Computer chip set for computer mother board referencing various clock rates 失效
标题翻译：计算机芯片组用于计算机主板，参考各种时钟频率
公开(公告)号：US06079027A
公开(公告)日：2000-06-20
申请号：US100515
申请日：1998-06-19
申请人： Jiin Lai , Heng-Chen Ho , Kuo-Ping Liu
发明人： Jiin Lai , Heng-Chen Ho , Kuo-Ping Liu
IPC分类号： G06F1/08 , G06F1/04
CPC分类号： G06F1/08
摘要： A computer chip set is devised for use on a computer mother board with at least two clock rates including a first clock rate and a second clock rate for the purpose of converting an input signal referencing either the first or second clock rate to an output signal referencing the other clock rate. The first and second clock rates are in virtual synchronism and have a fixed ratio between them. The computer chip set utilizes a phase signal generator capable of generating a set of phase signals and a signal conversion logic circuit for generating the output signal referencing one of the first and second clock rates other than the one referenced by the input signal. This computer chip set can allow the computer mother board to be operated without waiting a state so that the data processing efficiency of the computer mother board can be enhanced. A multiplexer means used in the computer chip set of the invention has an output which is selectively muliplexed between the first clock rate and the second clock rate to serve as a third clock signal. This computer chip set allows the designer to use a slower clock rate to drive the DRAM.
摘要翻译：计算机芯片组被设计为在具有至少两个时钟速率的计算机母板上使用，包括第一时钟速率和第二时钟速率，用于将参考第一或第二时钟速率的输入信号转换为参考的输出信号另一个时钟速率。第一和第二时钟速率是虚拟同步的，并且它们之间具有固定的比例。计算机芯片组利用能够产生一组相位信号的相位信号发生器和信号转换逻辑电路，用于产生参考第一和第二时钟速率之一的输出信号，而不是由输入信号所参考的那个。该计算机芯片组可以允许计算机母板在不等待状态的情况下操作，从而可以提高计算机母板的数据处理效率。在本发明的计算机芯片组中使用的多路复用器装置具有在第一时钟速率和第二时钟速率之间选择性地混合以用作第三时钟信号的输出。该计算机芯片组允许设计者使用较慢的时钟速率来驱动DRAM。

94. 发明授权

US6031752A Installation for providing constant loading in memory slot 失效
标题翻译：安装在内存插槽中提供恒定的加载
公开(公告)号：US6031752A
公开(公告)日：2000-02-29
申请号：US111034
申请日：1998-07-07
申请人： Jiin Lai , Ching-Fu Chuang
发明人： Jiin Lai , Ching-Fu Chuang
IPC分类号： G11C5/00 , G11C5/02
CPC分类号： G06F13/409
摘要： An installation inside a memory slot for providing a constant loading to an external signaling line with or without the insertion of a memory module into a memory slot. The installation operates by supplying a load element whose loading effect is roughly equivalent to the loading effect of a memory module when no memory module is plugged, and disconnecting the load element internally when a memory module is plugged into the memory slot. Hence, a constant loading is provided to the external signaling line no matter a memory module is plugged or not, and so signal quality and integrity of the signaling line can be maintained.
摘要翻译：存储器插槽内部的安装，用于通过或不将存储器模块插入到存储器插槽中来向外部信号线提供恒定的加载。当没有存储器模块插入时，通过提供负载效应大致等于存储器模块的负载效应的负载元件，并且当存储器模块插入到存储器插槽中时将该负载元件断开。因此，无论存储器模块是否被插入，都向外部信号线提供恒定的负载，因此可以保持信号线的信号质量和完整性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式