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91. 发明授权

US06670819B2 Methods of engaging electrically conductive pads on a semiconductor substrate 失效
公开(公告)号：US06670819B2
公开(公告)日：2003-12-30
申请号：US10057711
申请日：2002-01-24
申请人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
发明人： Warren M. Farnworth , Malcolm Grief , Gurtej S. Sandhu
IPC分类号： G01R3102
CPC分类号： G01R1/07314 , H01L2924/00013 , H05K1/0306 , H05K3/325 , H05K2201/0367 , H05K2201/0373 , H05K2201/09045 , Y10S438/978 , Y10T29/49117 , Y10T29/49204 , H01L2224/29099
摘要： A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

92. 发明授权

US06632343B1 Method and apparatus for electrolytic plating of surface metals 有权
标题翻译：表面金属的电解电镀方法和装置
公开(公告)号：US06632343B1
公开(公告)日：2003-10-14
申请号：US09651040
申请日：2000-08-30
申请人： Warren M. Farnworth , Kevin G. Duesman
发明人： Warren M. Farnworth , Kevin G. Duesman
IPC分类号： C25D502
CPC分类号： H05K3/242 , H05K1/0346 , H05K1/0373 , H05K3/243 , H05K2201/0154 , H05K2201/0323 , H05K2203/1142
摘要： A method and apparatus for electrolytic plating of selected areas of printed circuit board traces is disclosed. The method is characterized by its elimination of the need for plating bus bars and plating contacts on the printed circuit board to facilitate a spot-plating process. In one embodiment, a printed circuit board substrate is provided which is at least partially conductive, such that a plating voltage may be applied to any one or more points on the substrate during a spot plating operation. In another embodiment, the substrate material is initially partially conductive, but following the spot-plating operation, is subjected to a curing treatment or the like to cause degeneration of the substrate's conductivity. Carbon-impregnated polyimide, partially-cured polyimide, FR4 or FR5, with appropriate contaminants introduced therein are contemplated as materials suitable for a printed circuit board substrate in accordance with the invention. In another embodiment, the traces are first applied to the partially conductive substrate by an electroplating operation wherein an electroplating voltage is applied to the substrate such that the substrate itself serves as one terminal of the electroplating system.
摘要翻译：公开了一种用于印刷电路板迹线的选定区域的电解电镀的方法和装置。该方法的特征在于消除了对印刷电路板上的母线和电镀触点的需要，以便于电镀过程。在一个实施例中，提供至少部分导电的印刷电路板基板，使得可以在点电镀操作期间将电镀电压施加到基板上的任何一个或多个点。在另一个实施例中，基板材料最初是部分导电的，但是在电镀操作之后，进行固化处理等以使基板导电性变差。被浸入其中的合适污染物的碳浸渍的聚酰亚胺，部分固化的聚酰亚胺，FR4或FR5被考虑为适用于根据本发明的印刷电路板基底的材料。在另一个实施例中，通过电镀操作首先将迹线施加到部分导电衬底上，其中将电镀电压施加到衬底，使得衬底本身用作电镀系统的一个端子。

93. 发明授权

US06628128B1 CSP BGA test socket with insert and method 失效
公开(公告)号：US06628128B1
公开(公告)日：2003-09-30
申请号：US09651860
申请日：2000-08-30
申请人： Warren M. Farnworth , Derek J. Gochnour , David R. Hembree
发明人： Warren M. Farnworth , Derek J. Gochnour , David R. Hembree
IPC分类号： G01R3102
CPC分类号： H05K1/112 , G01R1/0483 , H05K3/325 , H05K2201/09472 , H05K2201/09827 , H05K2201/10734
摘要： A BGA test socket for use in standard testing and burn-in testing of BGA dies and method for testing such dies is disclosed wherein a die contact insert made of silicon or ceramic using standard IC fabrication technology is used. Through using such an insert, even small scale (pitch) BGA dies can be reliably tested including chip scale packaged (“CSP”) BGA dies. Furthermore, using such an insert allows a conventional socket to be adapted for use with a wide variety of both BGA dies and other varieties. A method for using the device is disclosed which overcomes current static electricity problems experienced in testing CSP BGA dies through closing the test socket before removing the die deposit probe.

94. 发明授权

US06619532B2 Methods to utilize ultrasonic energy to reduce the initial contact forces in known-good-die or permanent contact systems 有权
标题翻译：利用超声波能量来减少已知好的模具或永久接触系统中的初始接触力的方法
公开(公告)号：US06619532B2
公开(公告)日：2003-09-16
申请号：US10196666
申请日：2002-07-15
申请人： David R. Hembree , Michael E. Hess , John O. Jacobson , Warren M. Farnworth , Alan G. Wood
发明人： David R. Hembree , Michael E. Hess , John O. Jacobson , Warren M. Farnworth , Alan G. Wood
IPC分类号： B23K2010
CPC分类号： B23K20/10 , B23K2101/38
摘要： A machine and method for bonding puncture-type conductive contact members of an interconnect to the bond pads of a bare semiconductor die includes the use of one or two ultrasonic vibrators mounted to vibrate one or both of the die and interconnect. A short axial linear burst of ultrasonic energy enables the contact members to pierce hard oxide layers on the surfaces of the bond pads at a much lower compressive force and rapidly achieve full penetration depth.
摘要翻译：用于将互连的穿刺型导电接触构件接合到裸半导体管芯的接合焊盘的机器和方法包括使用安装成振动模具和互连中的一个或两者的一个或两个超声波振动器。超声能量的短轴向线性爆发使得接触构件能够以低得多的压缩力在接合焊盘的表面上刺穿硬氧化物层并且迅速地实现完全的穿透深度。

95. 发明授权

US06614104B2 Stackable semiconductor package having conductive layer and insulating layers 有权
标题翻译：具有导电层和绝缘层的可堆叠半导体封装
公开(公告)号：US06614104B2
公开(公告)日：2003-09-02
申请号：US10264047
申请日：2002-10-04
申请人： Warren M. Farnworth , Alan G. Wood , Mike Brooks
发明人： Warren M. Farnworth , Alan G. Wood , Mike Brooks
IPC分类号： H01L2302
CPC分类号： H01L24/06 , H01L24/97 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/48091 , H01L2224/4826 , H01L2224/73215 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00014 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a substrate and a semiconductor die wire bonded, or alternately flip chip bonded, to the substrate. The substrate includes three separate layers including a conductive layer having a pattern of conductive traces, a first insulating layer covering the conductive traces, and a second insulating layer covering the die. The insulating layers also include planar surfaces having external contacts, and conductive vias in electrical communication with the external contacts and with the conductive traces. The external contacts have matching patterns, such that the package can be stacked on a substantially identical package to form a stacked electronic assembly. In addition, the packages in the stacked assembly can have different circuit configurations, and can perform different functions in the assembly. A method for fabricating the package includes the steps of providing the conductive layer having the conductive traces, attaching the die to the conductive traces, forming the first insulating layer on the conductive layer, forming the second insulating layer on the die, forming the conductive vias through the insulating layers, and then forming the external contacts on the planar surfaces of the insulating layers.
摘要翻译：半导体封装包括基板和半导体芯片引线，该半导体芯片引线与基板接合或交替地倒装芯片接合。衬底包括三个分开的层，包括具有导电迹线图案的导电层，覆盖导电迹线的第一绝缘层和覆盖管芯的第二绝缘层。绝缘层还包括具有外部触点的平面表面，以及与外部触点和导电迹线电连通的导电通孔。外部触点具有匹配的图案，使得封装可以堆叠在基本相同的封装上以形成堆叠的电子组件。此外，堆叠组件中的封装可以具有不同的电路配置，并且可以在组件中执行不同的功能。制造封装的方法包括以下步骤：提供具有导电迹线的导电层，将裸片附着到导电迹线上，在导电层上形成第一绝缘层，在裸片上形成第二绝缘层，形成导电通孔通过绝缘层，然后在绝缘层的平坦表面上形成外部接触。

96. 发明授权

US06612872B2 Apparatus for forming modular sockets using flexible interconnects and resulting structures 失效
标题翻译：用于使用柔性互连和结构的结构形成模块化插座的装置
公开(公告)号：US06612872B2
公开(公告)日：2003-09-02
申请号：US10158979
申请日：2002-05-30
申请人： Warren M. Farnworth , David J. Corisis , Salman Akram
发明人： Warren M. Farnworth , David J. Corisis , Salman Akram
IPC分类号： H01R2370
CPC分类号： H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06593 , H01L2924/0002 , H01L2924/3011 , H01R12/57 , H01R12/7082 , H01R12/721 , H01R12/856 , H01R13/24 , H01R13/514 , H05K7/023 , Y10T29/49126 , Y10T29/4913 , Y10T29/49147 , Y10T29/49153 , Y10T29/49169 , Y10T29/49204 , Y10T29/49222 , H01L2924/00
摘要： A modular bare die socket assembly for attaching a plurality of miniature semiconductor dice to a substrate. The socket assembly is comprised of a plurality of two-sided plates joined vertically in a horizontal stack, wherein each plate has a die socket for the removable insertion of a bare semiconductor die. A multi-layer interconnect lead tape has a plurality of lithographically formed leads bent on one end to form nodes for attachment to bond pads on the removably inserted semiconductor die, and having opposing ends connectable to the substrate.
摘要翻译：一种用于将多个微型半导体管芯附接到衬底的模块裸露裸露插座组件。插座组件由在水平叠层中垂直连接的多个双面板组成，其中每个板具有用于可裸插入裸半导体管芯的管芯插座。多层互连引线带具有在一端弯曲的多个光刻形成的引线，以形成用于附接到可移除插入的半导体管芯上的接合焊盘并具有可连接到基板的相对端的节点。

97. 发明授权

US06593171B2 Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages 失效
公开(公告)号：US06593171B2
公开(公告)日：2003-07-15
申请号：US10074840
申请日：2002-02-13
申请人： Warren M. Farnworth
发明人： Warren M. Farnworth
IPC分类号： H01L2144
CPC分类号： B29C70/72 , B33Y10/00 , B33Y30/00 , B33Y80/00 , G03F7/70416 , H01L21/56 , H01L21/561 , H01L21/67126 , H01L23/29 , H01L23/291 , H01L23/3107 , H01L23/3121 , H01L23/4951 , H01L24/48 , H01L24/97 , H01L2224/05599 , H01L2224/16225 , H01L2224/274 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01049 , H01L2924/01074 , H01L2924/01082 , H01L2924/09701 , H01L2924/12042 , H01L2924/181 , H01L2924/351 , Y02P80/30 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A stereolithographically fabricated, substantially hermetic package surrounds at least a portion of a semiconductor die so as to substantially hermetically seal the same. Stereolithographic processes may be used to fabricate at least a portion of the substantially hermetic package from thermoplastic glass, other types of glass, ceramics, or metals. The substantially hermetic package may be used with semiconductor device assemblies or with bare or minimally packaged semiconductor dice, including dice that have yet to be singulated from a wafer. The stereolithographic method may include use of a machine vision system including at least one camera operably associated with a computer controlling a stereolithographic application of material so that the system may recognize the position, orientation, and features of a semiconductor device assembly, semiconductor die, or other substrate on which the substantially hermetic package is to be fabricated.

98. 发明授权

US06548392B2 Methods of a high density flip chip memory arrays 有权
标题翻译：高密度倒装芯片存储阵列的方法
公开(公告)号：US06548392B2
公开(公告)日：2003-04-15
申请号：US09398337
申请日：1999-09-17
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L2144
CPC分类号： H01L24/81 , H01L23/552 , H01L23/556 , H01L27/10897 , H01L2224/05001 , H01L2224/05027 , H01L2224/05572 , H01L2224/13111 , H01L2224/1319 , H01L2224/16 , H01L2224/274 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要： A low alpha emissivity-induced error solder bump, flip-chip integrated circuit device. The device includes a semiconductor die having an active surface and a bond pad array disposed about the active surface of the die. The active surface of the die includes logic circuits adjacent memory cell arrays. Each of the bond pads directly overlays a logic circuit, to which they may be connected. The present invention also includes methods for designing and fabricating the invented devices and connecting them to a carrier substrate.
摘要翻译：低α辐射率引起的误差焊料凸块，倒装芯片集成电路器件。该器件包括具有活动表面的半导体管芯和围绕管芯的有效表面设置的接合焊盘阵列。芯片的有源表面包括与存储单元阵列相邻的逻辑电路。每个接合焊盘直接覆盖它们可以连接到的逻辑电路。本发明还包括用于设计和制造本发明的装置并将其连接到载体基板的方法。

99. 发明授权

US06531345B2 Method and apparatus for fabricating electronic device 失效
标题翻译：用于制造电子设备的方法和装置
公开(公告)号：US06531345B2
公开(公告)日：2003-03-11
申请号：US09917695
申请日：2001-07-31
申请人： Warren M. Farnworth , Kevin G. Duesman , Alan G. Wood
发明人： Warren M. Farnworth , Kevin G. Duesman , Alan G. Wood
IPC分类号： H01L2182
CPC分类号： G11C29/88 , G11C5/063 , G11C29/006 , H01L22/22 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Logic circuitry formed in street areas between adjacent fabricated electronic devices may be used as auxiliary or redundant components to salvage one or more otherwise defective devices. Logic circuitry is selectively coupled to the defective device(s) to directly replace or facilitate the replacement of defective components on one or more fabricated devices, thereby resulting in a single operable electronic device. The invention may be used to increase the production yield of electronic devices, particularly, semiconductor integrated circuits. The invention permits the fabrication of discretionary wiring during the normal metalization of semiconductor layers to interconnect electronic devices at the same time as the formation of the normal wiring/circuitry of the devices.
摘要翻译：形成在相邻制造的电子设备之间的街道区域中的逻辑电路可以用作辅助或冗余组件来挽救一个或多个否则有缺陷的设备。逻辑电路选择性地耦合到有缺陷的装置，以直接替换或促进在一个或多个制造的装置上更换有缺陷的部件，由此导致单个可操作的电子装置。本发明可以用于增加电子设备，特别是半导体集成电路的生产成本。本发明允许在半导体层的正常金属化期间制造任意布线，以在形成设备的正常布线/电路的同时互连电子器件。

100. 发明授权

US06524346B1 Stereolithographic method for applying materials to electronic component substrates and resulting structures 有权
标题翻译：用于将材料应用于电子元件基板和所得结构的立体光刻方法
公开(公告)号：US06524346B1
公开(公告)日：2003-02-25
申请号：US09259143
申请日：1999-02-26
申请人： Warren M. Farnworth
发明人： Warren M. Farnworth
IPC分类号： H01L2131
CPC分类号： H01L23/544 , B33Y10/00 , H01L21/481 , H01L24/81 , H01L2223/54426 , H01L2223/54473 , H01L2224/8114 , H01L2224/81801 , H01L2924/12042 , H05K3/0023 , H05K3/28 , H05K3/303 , H05K2201/09909 , H05K2201/10636 , H05K2201/10674 , H05K2203/167 , Y02P70/611 , Y02P70/613 , H01L2924/00
摘要： A stereolithographic method of applying material to preformed electronic components with a high degree of precision, and resulting structures. A substrate used for effecting electrical testing of semiconductor dice or a carrier substrate for same may be provided with a protective structure in the form of at least one layer or segment of dielectric material having a controlled thickness or depth. The layer or segment may include precisely sized, shaped and located apertures through which conductive terminals on the surface of the substrate may be accessed. Dielectric material may also be employed as a structure to mechanically align the die with the substrate for proper communication of conductive connective elements projecting from a die with the substrate terminals, either in the form of the apertures in the dielectric material layer or segment on the substrate to partially receive the conductive connective elements, an alignment structure comprising upwardly-projecting alignment elements adjacent or bracketing an intended die location on the substrate, or both.
摘要翻译：以高精度将材料施加到预先形成的电子元件的立体光刻方法，以及所得到的结构。用于实现半导体芯片的电测试的基板或用于其的载体基板的基板可以设置有至少一层具有受控厚度或深度的介电材料层或段的形式的保护结构。层或片段可以包括精确尺寸的，形状和定位的孔，可以通过该孔到达衬底的表面上的导电端子。电介质材料也可以用作机械地对准管芯与衬底的结构，用于使导电连接元件从基片端子突出的导电连接元件以电介质材料层或衬底上的段的形式正确连通以部分地接收导电连接元件，对准结构包括向上突出的对准元件，邻近或包围基底上的预定的模具位置或两者。

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