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91. 发明申请

US20070069784A1 Open-loop slew-rate controlled output driver 有权
标题翻译：开环压摆率控制输出驱动器
公开(公告)号：US20070069784A1
公开(公告)日：2007-03-29
申请号：US11482684
申请日：2006-07-06
申请人： Dong-Suk Shin , In-Hwa Jung , Jin-Han Kim , Chulwoo Kim , Hyung-Dong Lee
发明人： Dong-Suk Shin , In-Hwa Jung , Jin-Han Kim , Chulwoo Kim , Hyung-Dong Lee
IPC分类号： H03K5/12
CPC分类号： H03K19/00384 , H03K17/163 , H03K17/6872 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A slew-rate controlled output driver for use in a semiconductor device includes a PVT variation detection unit having a delay line for receiving a reference clock in order to detect a delay amount variation of the delay line determined according to process, voltage and temperature (PVT) variation; a selection signal generation unit for generating a driving selection signal which corresponds to a detection signal generated by the PVT variation detection unit; and an output driving unit having a plurality of driver units controlled by an output data and the driving selection signal for driving an output terminal with a driving strength which corresponds to the PVT variation.
摘要翻译：用于半导体器件的转换速率控制输出驱动器包括具有用于接收参考时钟的延迟线的PVT变化检测单元，以便检测根据处理，电压和温度（PVT）确定的延迟线的延迟量变化）变异选择信号生成单元，用于产生对应于由PVT变化检测单元生成的检测信号的驱动选择信号; 以及输出驱动单元，其具有由输出数据控制的多个驱动器单元和用于以对应于PVT变化的驱动强度来驱动输出端子的驱动选择信号。

92. 发明申请

US20070059898A1 Semiconductor devices including trench isolation structures and methods of forming the same 审中-公开
标题翻译：包括沟槽隔离结构的半导体器件及其形成方法
公开(公告)号：US20070059898A1
公开(公告)日：2007-03-15
申请号：US11393546
申请日：2006-03-30
申请人： Dong-Suk Shin , Seung-Jin Lee , Yong-Kuk Jeong , Ki-Kwan Park
发明人： Dong-Suk Shin , Seung-Jin Lee , Yong-Kuk Jeong , Ki-Kwan Park
IPC分类号： H01L21/76
CPC分类号： H01L21/76229 , H01L21/76232
摘要： Trench isolation methods include forming a first trench and a second trench, having a larger width than the first trench, in a semiconductor substrate. A lower isolation layer is formed having a first thickness on an upper sidewall of the first trench and a second thickness on an upper sidewall of the second trench using a first high density plasma deposition process, the second thickness being greater than the first thickness. An upper isolation layer is formed on the semiconductor substrate including the lower isolation layer using a second high density plasma deposition process, different from the first high density plasma deposition process. The first and second high density plasma deposition processes may be chemical vapor deposition processes. Semiconductor devices including a trench isolation structure are also provided.
摘要翻译：沟槽隔离方法包括在半导体衬底中形成具有比第一沟槽更大的宽度的第一沟槽和第二沟槽。使用第一高密度等离子体沉积工艺在第一沟槽的上侧壁上形成具有第一厚度的第一厚度和在第二沟槽的上侧壁上的第二厚度的下隔离层，第二厚度大于第一厚度。使用不同于第一高密度等离子体沉积工艺的第二高密度等离子体沉积工艺在包括下隔离层的半导体衬底上形成上隔离层。第一和第二高密度等离子体沉积工艺可以是化学气相沉积工艺。还提供了包括沟槽隔离结构的半导体器件。

93. 发明申请

US20060131656A1 CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same 有权
标题翻译：具有升高的源极和漏极区域的CMOS半导体器件及其制造方法
公开(公告)号：US20060131656A1
公开(公告)日：2006-06-22
申请号：US11285978
申请日：2005-11-23
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/7834 , H01L21/265 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions. A second gate spacer is provided to cover edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern. Methods of fabricating the CMOS device is also provided.
摘要翻译：提供互补金属氧化物半导体（CMOS）器件。 CMOS器件包括设置在半导体衬底中以限定第一和第二有源区的隔离层。第一和第二栅极图案分别设置成跨越第一和第二有源区域。第一升高的源极区域和第一升高的漏极区域分别设置在第一栅极图案的两侧，并且第二升高的源极区域和第二升高的漏极区域分别设置在第二栅极图案的两侧。第一升高的源极/漏极区域设置在第一有源区上，而第二升高的源极/漏极区域设置在第二有源区域上。在第一栅极图案和第一升高的源极/漏极区域之间提供第一栅极间隔物。设置第二栅极间隔物以覆盖与第二栅极图案相邻的第二升高的源极/漏极区域和第二栅极图案的上侧壁的边缘。还提供了制造CMOS器件的方法。

94. 发明申请

US20060088968A1 Methods of fabricating a semiconductor device using a selective epitaxial growth technique 有权
标题翻译：使用选择性外延生长技术制造半导体器件的方法
公开(公告)号：US20060088968A1
公开(公告)日：2006-04-27
申请号：US11299447
申请日：2005-12-08
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an epitaxial semiconductor layer on a sidewall and on a bottom surface of the recess. A selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxial semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the semiconductor substrate.
摘要翻译：使用选择性外延生长技术制造半导体器件的方法包括在半导体衬底中形成凹部。将具有凹部的基板装入反应室。将半导体源气体和主蚀刻气体注入到反应室中，以选择性地在凹槽的侧壁和底表面上生长外延半导体层。选择性蚀刻气体被注入到反应室中，以选择性地蚀刻外延半导体层的与凹槽的侧壁相邻的栅栏，并生长到高于半导体衬底的上表面的水平。

95. 发明申请

US20060038230A1 Transistor and method of manufacturing the same 有权
公开(公告)号：US20060038230A1
公开(公告)日：2006-02-23
申请号：US11207703
申请日：2005-08-19
申请人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee , Dong-Suk Shin , Seung-Hwan Lee
发明人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee , Dong-Suk Shin , Seung-Hwan Lee
IPC分类号： H01L27/12 , H01L29/06
CPC分类号： H01L29/66636 , H01L29/045 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7834
摘要： A transistor includes a semiconductor substrate that has a first surface of a {100} crystal plane, a second surface of the {100} crystal plane having a height lower than that of the first surface, and a third surface of a {111} crystal plane connecting the first surface to the second surface. First heavily doped impurity regions are formed under the second surface. A gate structure is formed on the first surface. An epitaxial layer is formed on the second surface and the third surface. Second heavily doped impurity regions are formed at both sides of the gate structure. The second heavily doped impurity regions have side faces of the {111} crystal plane so that a short channel effect generated between the impurity regions may be prevented.

96. 发明申请

US20060008961A1 Method of forming MOS transistor having fully silicided metal gate electrode 有权
公开(公告)号：US20060008961A1
公开(公告)日：2006-01-12
申请号：US11158978
申请日：2005-06-22
申请人： Seung-Hwan Lee , Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee
发明人： Seung-Hwan Lee , Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： Methods of fabricating a MOS transistor having a fully silicided metal gate electrode are provided. The method includes forming an isolation layer in a predetermined region of a semiconductor substrate to define an active region. An insulated gate pattern which crosses over the active region is formed. A spacer is formed on sidewalls of the gate pattern. A selective epitaxial growth process is applied to form semiconductor layers on the gate pattern and on the active region at both sides of the gate pattern. In this case, a poly-crystalline semiconductor layer is formed on the gate pattern while single-crystalline semiconductor layers are concurrently formed on the active region at both sides of the gate pattern. The semiconductor layers are selectively etched to form a gate-reduced pattern and elevated source and drain regions. Respective desired thicknesses of the gate-reduced pattern and the elevated source and drain regions may be obtained using an etch selectivity between the poly-crystalline semiconductor layer and the single-crystalline semiconductor layer. A silicidation process is applied to the semiconductor substrate where the gate-reduced pattern is formed to simultaneously form a fully silicided metal gate electrode and elevated source and drain silicide layers.

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