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91. 发明申请

US20120112045A1 SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING TRANSISTOR 有权
标题翻译：半导体器件和驱动晶体管的方法
公开(公告)号：US20120112045A1
公开(公告)日：2012-05-10
申请号：US13282505
申请日：2011-10-27
申请人： Masashi TSUBUKU , Kengo AKIMOTO
发明人： Masashi TSUBUKU , Kengo AKIMOTO
IPC分类号： H01L31/08 , H03K17/687
CPC分类号： H01L27/1225 , G02F1/1368 , G06F3/038 , G09F9/30 , G09G3/3648 , G09G2360/142
摘要： When a positive bias voltage is applied to a gate electrode of a transistor including an oxide semiconductor for longer than or equal to 10 msec, electric characteristics of the transistor, which have varied due to the light irradiation, can be brought to the state which is substantially the same as the state before the light irradiation. Note that a positive bias voltage is applied to the gate electrode of the transistor at an appropriate timing with reference to the amount of incident light received by the transistor. Accordingly, a display device in which a reduction in display quality is suppressed even when light irradiation is performed can be realized.
摘要翻译：当正偏压被施加到包括氧化物半导体的晶体管的栅电极长于或等于10毫秒时，由于光照射而变化的晶体管的电特性可以变为基本上与光照射前的状态相同。注意，在相应于由晶体管接收的入射光量的适当时刻，正偏置电压施加到晶体管的栅电极。因此，即使在进行光照射时也能够抑制显示品质的降低的显示装置。

92. 发明申请

US20120058600A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120058600A1
公开(公告)日：2012-03-08
申请号：US13292207
申请日：2011-11-09
申请人： Hideaki KUWABARA , Kengo AKIMOTO , Toshinari SASAKI
发明人： Hideaki KUWABARA , Kengo AKIMOTO , Toshinari SASAKI
IPC分类号： H01L21/34
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/04 , H01L29/24 , H01L29/458 , H01L29/4908 , H01L29/78696
摘要： An object is to increase field effect mobility of a thin film transistor including an oxide semiconductor. Another object is to stabilize electrical characteristics of the thin film transistor. In a thin film transistor including an oxide semiconductor layer, a semiconductor layer or a conductive layer having higher electrical conductivity than the oxide semiconductor is formed over the oxide semiconductor layer, whereby field effect mobility of the thin film transistor can be increased. Further, by forming a semiconductor layer or a conductive layer having higher electrical conductivity than the oxide semiconductor between the oxide semiconductor layer and a protective insulating layer of the thin film transistor, change in composition or deterioration in film quality of the oxide semiconductor layer is prevented, so that electrical characteristics of the thin film transistor can be stabilized.
摘要翻译：目的是增加包括氧化物半导体的薄膜晶体管的场效应迁移率。另一个目的是稳定薄膜晶体管的电特性。在包括氧化物半导体层的薄膜晶体管中，在氧化物半导体层上形成具有比氧化物半导体更高的导电性的半导体层或导电层，由此可以提高薄膜晶体管的场效应迁移率。此外，通过在氧化物半导体层和薄膜晶体管的保护绝缘层之间形成具有比氧化物半导体更高的导电性的半导体层或导电层，防止氧化物半导体层的组成变化或膜质量的劣化，使得薄膜晶体管的电特性能够稳定。

93. 发明申请

US20120043549A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120043549A1
公开(公告)日：2012-02-23
申请号：US13288995
申请日：2011-11-04
申请人： Kengo AKIMOTO
发明人： Kengo AKIMOTO
IPC分类号： H01L29/04 , H01L29/772 , H01L29/788
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L29/665 , H01L29/66825 , H01L29/7883
摘要： The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer, a first gate electrode, a second insulating layer, and a second gate electrode which are layered over the semiconductor layer in that order. Part or all of the source and drain regions is formed using a metal silicide layer. The first gate electrode contains a noble gas element.
摘要翻译：本发明涉及一种包括半导体层的非易失性半导体存储器件，该半导体层具有设置在源区和漏区之间的源极区，漏极区和沟道形成区; 以及依次层叠在半导体层上的第一绝缘层，第一栅电极，第二绝缘层和第二栅电极。源区和漏区的部分或全部使用金属硅化物层形成。第一栅电极包含惰性气体元件。

94. 发明申请

US20110291089A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110291089A1
公开(公告)日：2011-12-01
申请号：US13207449
申请日：2011-08-11
申请人： Kengo AKIMOTO , Masashi TSUBUKU
发明人： Kengo AKIMOTO , Masashi TSUBUKU
IPC分类号： H01L29/04 , H01L21/20
CPC分类号： H01L29/66742 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/324 , H01L21/447 , H01L27/1225 , H01L27/127 , H01L29/7869
摘要： To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode layers is small, the surfaces of the source and drain electrode layers are subjected to sputtering treatment with plasma and an oxide semiconductor layer containing In, Ga, and Zn is formed successively over the source and drain electrode layers without exposure of the source and drain electrode layers to air.
摘要翻译：为了提供一种制造薄膜晶体管的方法，其中氧化物半导体层和源极和漏极电极层之间的接触电阻小，源极和漏极电极层的表面用等离子体和氧化物半导体层进行溅射处理，所述氧化物半导体层含有 In，Ga和Zn依次形成在源极和漏极电极层上，而不会将源极和漏极电极层暴露于空气。

95. 发明申请

US20110221475A1 LOGIC CIRCUIT 有权
标题翻译：逻辑电路
公开(公告)号：US20110221475A1
公开(公告)日：2011-09-15
申请号：US13116372
申请日：2011-05-26
申请人： Jun KOYAMA , Kengo AKIMOTO , Masashi TSUBUKU
发明人： Jun KOYAMA , Kengo AKIMOTO , Masashi TSUBUKU
IPC分类号： H03K19/0944 , H01L27/088
CPC分类号： H03K19/094 , H01L27/0883 , H01L27/1225 , H03K19/09407 , H03K19/09421 , H03K19/096
摘要： An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.
摘要翻译：目的是将使用氧化物半导体的晶体管施加到包括增强晶体管的逻辑电路。逻辑电路包括耗尽晶体管101和增强晶体管102.晶体管101和102各自包括栅电极，栅极绝缘层，第一氧化物半导体层，第二氧化物半导体层，源电极和漏电极。晶体管102包括在源电极和漏极之间的第一氧化物半导体层中的区域上设置的还原防止层。

96. 发明申请

US20100314624A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100314624A1
公开(公告)日：2010-12-16
申请号：US12861977
申请日：2010-08-24
申请人： Kengo AKIMOTO
发明人： Kengo AKIMOTO
IPC分类号： H01L29/788 , H01L29/786 , H01L29/78
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L29/665 , H01L29/66825 , H01L29/7883
摘要： The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer, a first gate electrode, a second insulating layer, and a second gate electrode which are layered over the semiconductor layer in that order. Part or all of the source and drain regions is formed using a metal silicide layer. The first gate electrode contains a noble gas element.
摘要翻译：本发明涉及一种包括半导体层的非易失性半导体存储器件，该半导体层具有设置在源区和漏区之间的源极区，漏极区和沟道形成区; 以及依次层叠在半导体层上的第一绝缘层，第一栅电极，第二绝缘层和第二栅电极。源区和漏区的部分或全部使用金属硅化物层形成。第一栅电极包含惰性气体元件。

97. 发明申请

US20100117086A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造半导体器件的半导体器件和方法
公开(公告)号：US20100117086A1
公开(公告)日：2010-05-13
申请号：US12612006
申请日：2009-11-04
申请人： Kengo AKIMOTO , Masashi TSUBUKU
发明人： Kengo AKIMOTO , Masashi TSUBUKU
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/41733
摘要： An object is to suppress deterioration of element characteristics even when an oxide semiconductor is formed after a gate insulating layer, a source electrode layer, and a drain electrode layer are formed. A gate electrode layer is formed over a substrate. A gate insulating layer is formed over the gate electrode layer. A source electrode layer and a drain electrode layer are formed over the gate insulating layer. Surface treatment is performed on surfaces of the gate insulating layer, the source electrode layer, and the drain electrode layer which are formed over the substrate. After the surface treatment is performed, an oxide semiconductor layer is formed over the gate insulating layer, the source electrode layer, and the drain electrode layer.
摘要翻译：即使在形成了栅极绝缘层，源极电极层和漏极电极层之后形成氧化物半导体，也是要抑制元件特性的劣化。在基板上形成栅极电极层。在栅电极层上形成栅极绝缘层。源极电极层和漏电极层形成在栅绝缘层上。在形成在基板上的栅极绝缘层，源极电极层和漏极电极层的表面上进行表面处理。在进行表面处理之后，在栅极绝缘层，源极电极层和漏极电极层上形成氧化物半导体层。

98. 发明申请

US20100117076A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造半导体器件的半导体器件和方法
公开(公告)号：US20100117076A1
公开(公告)日：2010-05-13
申请号：US12612711
申请日：2009-11-05
申请人： Kengo AKIMOTO , Masashi TSUBUKU
发明人： Kengo AKIMOTO , Masashi TSUBUKU
IPC分类号： H01L29/786 , H01L21/336 , H01L29/12
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/42384 , H01L29/66969
摘要： It is disclosed that a semiconductor device includes an oxide semiconductor layer provided over a gate insulating layer, a source electrode layer, and a drain electrode layer, in which a thickness of the gate insulating layer located in a region between the source electrode layer and the drain electrode layer is smaller than a thickness of the gate insulating layer provided between the gate electrode layer and at least one of the source electrode layer and the drain electrode layer.
摘要翻译：公开了半导体器件包括设置在栅极绝缘层，源极电极层和漏极电极层上的氧化物半导体层，其中栅极绝缘层的厚度位于源极电极层和源极电极层之间的区域中漏极电极层的厚度小于设置在栅电极层与源极电极层和漏极电极层中的至少一个之间的栅极绝缘层的厚度。

99. 发明申请

US20100109708A1 LOGIC CIRCUIT 有权
标题翻译：逻辑电路
公开(公告)号：US20100109708A1
公开(公告)日：2010-05-06
申请号：US12605607
申请日：2009-10-26
申请人： Jun KOYAMA , Kengo AKIMOTO , Masashi TSUBUKU
发明人： Jun KOYAMA , Kengo AKIMOTO , Masashi TSUBUKU
IPC分类号： H03K19/096 , H01L27/088
CPC分类号： H03K19/094 , H01L27/0883 , H01L27/1225 , H03K19/09407 , H03K19/09421 , H03K19/096
摘要： An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.
摘要翻译：目的是将使用氧化物半导体的晶体管施加到包括增强晶体管的逻辑电路。逻辑电路包括耗尽晶体管101和增强晶体管102.晶体管101和102各自包括栅电极，栅极绝缘层，第一氧化物半导体层，第二氧化物半导体层，源电极和漏电极。晶体管102包括在源电极和漏极之间的第一氧化物半导体层中的区域上设置的还原防止层。

100. 发明申请

US20100055832A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100055832A1
公开(公告)日：2010-03-04
申请号：US12549603
申请日：2009-08-28
申请人： Kengo AKIMOTO , Masashi TSUBUKU
发明人： Kengo AKIMOTO , Masashi TSUBUKU
IPC分类号： H01L21/36
CPC分类号： H01L29/66742 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/324 , H01L21/447 , H01L27/1225 , H01L27/127 , H01L29/7869
摘要： To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode layers is small, the surfaces of the source and drain electrode layers are subjected to sputtering treatment with plasma and an oxide semiconductor layer containing In, Ga, and Zn is formed successively over the source and drain electrode layers without exposure of the source and drain electrode layers to air.
摘要翻译：为了提供一种制造薄膜晶体管的方法，其中氧化物半导体层和源极和漏极电极层之间的接触电阻小，源极和漏极电极层的表面用等离子体和氧化物半导体层进行溅射处理，所述氧化物半导体层含有 In，Ga和Zn依次形成在源极和漏极电极层上，而不会将源极和漏极电极层暴露于空气。

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