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91. 发明申请

US20070004643A1 Alpha-ketoamide derivative, and production method and use thereof 有权
标题翻译： α-酮酰胺衍生物及其制备方法和用途
公开(公告)号：US20070004643A1
公开(公告)日：2007-01-04
申请号：US10582015
申请日：2004-12-08
申请人： Yoshihisa Shirasaki , Hiroyuki Miyashita , Masayuki Nakamura , Jun Inoue
发明人： Yoshihisa Shirasaki , Hiroyuki Miyashita , Masayuki Nakamura , Jun Inoue
IPC分类号： A61K38/04 , C07K5/04
CPC分类号： C07D213/30 , C07C271/22 , C07C2601/02 , C07C2601/04 , C07C2602/08 , C07D295/215 , C07D307/20 , C07D309/12
摘要： The present invention provides a compound represented by the formula (I): (wherein R1 is a lower alkyl substituted by a lower alkoxy or a heterocyclic group, or a heterocyclic group; R2 is a lower alkyl optionally substituted by a phenyl; and R3 is a lower alkyl optionally substituted by a halogen, a lower alkoxy or a phenyl, or a fused polycyclic hydrocarbon group), which is well absorbed orally, exhibits durability of good blood level and has potent calpain inhibitory activity.
摘要翻译：本发明提供由式（I）表示的化合物：其中R 1是被低级烷氧基或杂环基或杂环基取代的低级烷基; R 2， / SUP>是任选被苯基取代的低级烷基; R 3是任选被卤素，低级烷氧基或苯基或稠合多环烃基取代的低级烷基，其是良好的口腔吸收，具有良好的血液水平的耐久性，并具有强大的钙蛋白酶抑制活性。

92. 发明申请

US20060090736A1 Flow damper for common rail fuel injection apparatus 失效
标题翻译：共轨燃油喷射装置用流量阻尼器
公开(公告)号：US20060090736A1
公开(公告)日：2006-05-04
申请号：US11261589
申请日：2005-10-31
申请人： Tadashi Nishiwaki , Hiroyuki Yokoya , Masayuki Nakamura
发明人： Tadashi Nishiwaki , Hiroyuki Yokoya , Masayuki Nakamura
IPC分类号： F02M69/46
CPC分类号： F02M63/0028 , F02M55/005 , F02M55/02 , F02M55/025 , F02M63/004 , F02M2200/31
摘要： A flow damper is provided with a clearance to absorb a deformation occurring in proximate to a lower end of the valve body by the clearance on an entire outer circumference of a lower side of a large diameter portion of a piston. By the configuration in this manner, even if the slight deviation in the accuracy or the shape of the seat surface occurs a radially inward deformation of a lower portion of the valve body when the valve body is fastened to the common rail body at a large axial force, the clearance absorbs the deformation. Thus, the deformation of the valve body does not affect the piston sliding hole. Accordingly, a sliding clearance of the piston does not change, not to spoil a slide motion of the piston.
摘要翻译：流动阻尼器具有间隙，以通过在活塞的大直径部分的下侧的整个外周上的间隙吸收在阀体的下端附近发生的变形。通过这样的结构，即使当阀体以大的轴向紧固到共轨体上时，阀体的精度或形状的轻微偏差发生在阀体的下部的径向向内变形力，间隙吸收变形。因此，阀体的变形不影响活塞滑动孔。因此，活塞的滑动间隙不变化，不会破坏活塞的滑动运动。

93. 再颁专利

USRE38944E1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：USRE38944E1
公开(公告)日：2006-01-24
申请号：US09974962
申请日：2001-10-12
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and columns selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。子存储垫上面是：主字线和列选择信号线与正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

94. 发明申请

US20050216061A1 Medical chair 失效
标题翻译：医疗椅
公开(公告)号：US20050216061A1
公开(公告)日：2005-09-29
申请号：US10924949
申请日：2004-08-25
申请人： Sang Kim , Masayuki Nakamura
发明人： Sang Kim , Masayuki Nakamura
IPC分类号： A61G15/12 , A61G15/02 , A61G15/04 , A61G15/06 , A61G15/10 , A61H1/00 , A61H1/02
CPC分类号： A61H1/008 , A61H1/0218 , A61H2201/1607 , A61H2201/1614 , A61H2201/163 , A61H2203/0431
摘要： A medical chair is provided which is useful in the case where the dental arch and the occlusal condition are to be measured correctly, and also in various medical treatment methods that synthetically pursue the balance of a human body, and which can relax muscular tension of the human body as much as possible in a condition where the human body extends along the direction of gravity while ensuring physiological curvature of the individual vertebrae. The medical chair has cranium position regulating means 7 and pelvis position regulating means 4 for respectively regulating the positions of the cranium and pelvis of a subject who sits on a seat. The regulating means 7 and 4 have a structure in which they butt against both right and left sides of the cranium and the pelvis, respectively to cause both planes centered in a right-and-left direction of the cranium and the pelvis to be in a same central plane which extends in the direction of gravity. An ideal condition of the body of the subject in which vertical and horizontal balances are achieved against the force of gravity can be achieved to ensure physiological curvature of vertebrae, and the condition can be maintained.
摘要翻译：提供了一种医疗椅，其在牙弓和咬合条件被正确测量的情况下也是有用的，并且在各种医疗处理方法中合成地追求人体的平衡，并且可以放松肌肉紧张人体尽可能地在人体沿着重力方向延伸的状态下，同时确保各个椎骨的生理性弯曲。医疗椅具有头颅位置调节装置7和骨盆位置调节装置4，用于分别调节坐在座位上的受试者的颅骨和骨盆的位置。调节装置7和4具有这样的结构，它们分别对接头骨和骨盆的右侧和左侧，使得以颅骨和骨盆的左右方向为中心的两个平面处于相同的中心平面在重力方向上延伸。可以实现对抗重力的垂直和水平平衡的主体的理想状态，以确保椎体的生理曲率，并且可以维持该状态。

95. 发明授权

US06680875B2 Semiconductor device, such as a synchronous DRAM, including a control circuit for reducing power consumption 有权
标题翻译：诸如同步DRAM的半导体器件，包括用于降低功耗的控制电路
公开(公告)号：US06680875B2
公开(公告)日：2004-01-20
申请号：US10259579
申请日：2002-09-30
申请人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
IPC分类号： G11C800
CPC分类号： G11C5/063 , G11C5/14 , G11C5/147 , G11C7/1072 , G11C8/12 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A semiconductor device comprising a plurality of memory banks and a plurality of power supply circuits corresponding to the memory banks. Each of the memory banks is independently activated by an activating command. Given an externally supplied voltage, each of the power supply circuits outputs a predetermined internal supply voltage. Each power supply circuit has its output connected to the corresponding memory bank. In response to a command for activating one of the memory banks, the corresponding power supply circuit is activated while the remaining power supply circuits is deactivated.
摘要翻译：一种半导体器件，包括多个存储体和对应于存储体的多个电源电路。每个存储体被激活命令独立地激活。给定外部提供的电压，每个电源电路输出预定的内部电源电压。每个电源电路的输出连接到相应的存储体。响应于用于激活存储体之一的命令，相应的电源电路被激活，而剩余的电源电路被去激活。

96. 发明授权

US06643923B1 Processes for manufacturing flexible wiring boards 失效
标题翻译：制造柔性布线板的工艺
公开(公告)号：US06643923B1
公开(公告)日：2003-11-11
申请号：US09744572
申请日：2001-02-28
申请人： Hiroyuki Hishinuma , Hideyuki Kurita , Ryo Ito , Masayuki Nakamura
发明人： Hiroyuki Hishinuma , Hideyuki Kurita , Ryo Ito , Masayuki Nakamura
IPC分类号： H05K302
CPC分类号： H05K3/4007 , H01L21/4853 , H01L21/4857 , H01L23/4985 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H05K3/423 , H05K3/4647 , H05K2201/0154 , H05K2201/0195 , H05K2201/0347 , H05K2201/0355 , H05K2201/0367 , H05K2201/09481 , H05K2201/09563 , H05K2203/0759 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49147 , Y10T29/49155 , H01L2224/05624 , H01L2924/00014
摘要： A process for manufacturing a flexible wiring board according to the present invention includes growing metal bumps (16) using a mask film patterned by photolithography. Fine openings are formed in a polyimide film with good precision allowing fine metal bumps (16) to be formed with good precision. After metal bumps (16) have been formed, the mask film is removed and a liquid resin material is applied and dried to form a coating, which is then cured into a resin film. The coating can be etched at surface portions during coating stage to expose the tops of metal bumps (16).
摘要翻译：根据本发明的柔性线路板的制造方法包括使用通过光刻图案化的掩模膜生长金属凸块（16）。在聚酰亚胺膜中形成精细的开口，精度高，能够精确地形成精细的金属凸块（16）。在形成金属凸块（16）之后，除去掩模膜并施加液体树脂材料并干燥以形成涂层，然后将其固化成树脂膜。涂层可以在涂覆阶段在表面部分进行蚀刻以暴露金属凸块（16）的顶部。

97. 发明授权

US06583364B1 Ultrasonic manufacturing apparatuses, multilayer flexible wiring boards and processes for manufacturing multilayer flexible wiring boards 有权
标题翻译：超声波制造装置，多层柔性布线板以及多层挠性布线板的制造方法
公开(公告)号：US06583364B1
公开(公告)日：2003-06-24
申请号：US09642638
申请日：2000-08-22
申请人： Hideyuki Kurita , Masanao Watanabe , Masayuki Nakamura , Mitsuhiro Fukuda , Hiroyuki Usui
发明人： Hideyuki Kurita , Masanao Watanabe , Masayuki Nakamura , Mitsuhiro Fukuda , Hiroyuki Usui
IPC分类号： H05K100
CPC分类号： H05K3/4635 , H01L2224/1147 , H01L2924/01019 , H05K1/0393 , H05K3/005 , H05K3/28 , H05K3/423 , H05K3/4617 , H05K3/4647 , H05K3/4652 , H05K2201/0195 , H05K2201/0355 , H05K2201/09563 , H05K2203/0195 , H05K2203/0285 , H05K2203/1189 , Y10T29/49124 , Y10T29/49126 , Y10T29/49155
摘要： The present invention pertains to a multilayer flexible wiring board. The multilayer flexible wiring board including first and second patterned wiring layers, a resin film interposed between a surface of the first wiring layer and a surface of the second wiring layer, and a bump connected to the surface of the second wiring layer, wherein the resin film is adapted to form an opening when the bump to force into the resin film and an ultrasonic wave is applied to the bump and the bump is left in the opening to electrically connect the top of the bump to the first wiring layer.
摘要翻译：本发明涉及一种多层柔性布线板。多层挠性布线板包括第一和第二图案化布线层，介于第一布线层的表面和第二布线层的表面之间的树脂膜和连接到所述第二布线层的表面，其中当所述凸起压入所述树脂膜中时，所述树脂膜适于形成开口，并且超声波被施加到所述凸起，并且所述凸块被留在所述开口中以电连接所述第二布线层的顶部碰到第一个接线层。

98. 发明授权

US6088252A Semiconductor storage device with an improved arrangement of electrodes and peripheral circuits to improve operational speed and integration 有权
标题翻译：半导体存储器件具有改进的电极和外围电路的布置，以提高操作速度和集成度
公开(公告)号：US6088252A
公开(公告)日：2000-07-11
申请号：US177889
申请日：1998-10-23
申请人： Hiroki Fujisawa , Masayuki Nakamura
发明人： Hiroki Fujisawa , Masayuki Nakamura
IPC分类号： G11C11/401 , G11C5/02 , G11C8/10 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108
CPC分类号： G11C8/10 , G11C5/025
摘要： A semiconductor storage device is provided in which electrodes are provided so as to be arranged in the central portion so as to divide a semiconductor chip into two segments, an address buffer is provided neighboring those electrodes which receive address signals among said electrodes, memory arrays are constituted so as to be divided into at least two groups sandwiching said central portion, an address decoder is provided on a peripheral side of the semiconductor chip opposite to the central portion where the electrodes of the semiconductor chip are formed, and a predecoder for decoding the address signals is arranged on an intermediate portion extending from said central portion to a portion where said address decoder is provided.
摘要翻译：提供一种半导体存储装置，其中设置电极以便将半导体芯片分成两个部分，将这些电极设置在中心部分中，与在这些电极之间接收地址信号的那些电极相邻设置地址缓冲器，存储器阵列是被构造成被分成夹持所述中心部分的至少两个组，地址解码器设置在半导体芯片的与形成半导体芯片的电极的中心部分相对的周边，以及用于对地址信号被布置在从所述中心部分延伸到提供所述地址解码器的部分的中间部分上。

99. 发明授权

US6057290A Angiogenesis inhibitor 失效
标题翻译：血管生成抑制剂
公开(公告)号：US6057290A
公开(公告)日：2000-05-02
申请号：US740069
申请日：1996-10-24
申请人： Chiho Fukiage , Mitsuyoshi Azuma , Jun Inoue , Masayuki Nakamura , Yuka Yoshida
发明人： Chiho Fukiage , Mitsuyoshi Azuma , Jun Inoue , Masayuki Nakamura , Yuka Yoshida
IPC分类号： A61K38/55 , C07C311/19 , C07D303/48 , A61K38/00 , C07K5/00 , C07K7/00
CPC分类号： A61K38/55 , C07C311/19 , C07D303/48
摘要： An angiogenesis inhibitor comprising a cysteine protease inhibitory compound. As the preferable cysteine protease inhibitory compound, epoxysuccinic acid compounds, peptide halohydrazide compounds, calpain inhibitory compounds, compounds of the formula (I) ##STR1## and compounds of the formula (VI) ##STR2## can be used. The angiogenesis inhibitor of the present invention suppresses new formation of blood vessels in the living tissues, so that it can be used as a superior therapeutic or prophylactic agent of angiogenesis associated with wound healing, inflammation, growth of tumor and the like; and angiogenesis as seen in diabetic retinopathy, prematurity retinopathy, retinal venous occlusion, senile discoid macular degeneration and the like, as well as for prevention of metastasis of tumors.
摘要翻译：一种包含半胱氨酸蛋白酶抑制化合物的血管生成抑制剂。作为优选的半胱氨酸蛋白酶抑制化合物，可以使用环氧琥珀酸化合物，肽卤代酰肼化合物，钙蛋白酶抑制化合物，式（I）的化合物和式（VI）的化合物。本发明的血管发生抑制剂抑制活组织中血管的新形成，可以用作与伤口愈合，炎症，肿瘤生长等有关的血管生成的优异治疗或预防剂。和血管生成，如糖尿病视网膜病变，早产儿视网膜病变，视网膜静脉闭塞，老年性盘状黄斑变性等，以及用于预防肿瘤转移。

100. 发明授权

US5966341A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US5966341A
公开(公告)日：1999-10-12
申请号：US982398
申请日：1997-12-02
申请人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
发明人： Tsugio Takahashi , Goro Kitsukawa , Takesada Akiba , Yasushi Kawase , Masayuki Nakamura
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C11/4097 , H01L21/8242 , H01L27/105 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10805 , G11C11/408 , G11C11/4096 , G11C11/4097 , G11C7/10 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译：具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。子存储垫以格子排列。在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。

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