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1. 发明授权

US08422263B2 Load reduced memory module and memory system including the same 有权
标题翻译：负载减少的内存模块和包含相同的内存系统
公开(公告)号：US08422263B2
公开(公告)日：2013-04-16
申请号：US12801326
申请日：2010-06-03
申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
发明人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
IPC分类号： G11C5/06
CPC分类号： G11C7/00 , G11C5/02 , G11C5/04 , G11C5/063 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/109 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片，多个数据寄存器缓冲器以及安装在模块PCB上的命令/地址/控制寄存器缓冲器。数据寄存器缓冲器与存储器芯片执行数据传输。命令/地址/控制寄存器缓冲器执行命令/地址/控制信号的缓冲并产生控制信号。缓冲的命令/地址/控制信号被提供给存储器芯片，并且控制信号被提供给数据寄存器缓冲器。根据本发明，由于数据寄存器缓冲器和存储器芯片之间的线路长度被缩短，可以实现相当高的数据传输速率。

2. 发明授权

US07541862B2 Reference voltage generating circuit 有权
标题翻译：基准电压发生电路
公开(公告)号：US07541862B2
公开(公告)日：2009-06-02
申请号：US11603121
申请日：2006-11-22
申请人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
发明人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/30
摘要： A reference voltage generating circuit is described. The circuit includes a current generating section that generates a first current having a positive temperature coefficient, a voltage generating section that generates a voltage having a negative temperature coefficient, a synthesis section that generates a voltage which is the sum of a voltage having a positive temperature coefficient and developed across both terminals of a resistor, where the voltage has a negative temperature coefficient, and a compensation current generating section that generates a second current having a positive temperature coefficient. The current corresponding to the sum of said first and second currents is caused to flow through the resistor. The synthesis section generates a voltage which is a sum of a terminal voltage of the resistor by the sum current of the first and second currents and the voltage having a negative temperature coefficient.
摘要翻译：描述参考电压产生电路。该电路包括产生具有正温度系数的第一电流的电流产生部分，产生具有负温度系数的电压的电压产生部分，产生与具有正温度的电压之和的电压的合成部分系数，并且在电压具有负温度系数的电阻器的两端开发，以及产生具有正温度系数的第二电流的补偿电流产生部。使与第一和第二电流之和相对应的电流流过电阻器。合成部分产生电阻的端点电压与第一和第二电流的和电流与负温度系数的电压之和的电压。

3. 发明授权

US06512719B2 Semiconductor memory device capable of outputting and inputting data at high speed 有权
标题翻译：能够高速输出和输入数据的半导体存储器件
公开(公告)号：US06512719B2
公开(公告)日：2003-01-28
申请号：US09897997
申请日：2001-07-05
申请人： Hiroki Fujisawa , Masayuki Nakamura
发明人： Hiroki Fujisawa , Masayuki Nakamura
IPC分类号： G11C818
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1069 , G11C7/18
摘要： First and second data is transferred in parallel through a first signal transmission path, amplified by first and second relay amplification circuits, and transmitted via a second signal transmission path to first and second output registers, and an output circuit is provided for serially outputting the first and second data held by the first and second output registers, respectively, on the basis of address information. With respect to data to be outputted first of the first and second data, output timing of the data to be outputted later is delayed, data to be outputted first is made to correspond to the first output register, data to be outputted later is made to correspond to the second output register, and the transfer rate of the second signal transmission path corresponding to the first output register is set higher than that of the second signal transmission path corresponding to the second output register.
摘要翻译：第一和第二数据通过第一信号传输路径并行传送，由第一和第二继电器放大电路放大，并经由第二信号传输路径发送到第一和第二输出寄存器，并且提供输出电路用于串行输出第一以及分别由第一和第二输出寄存器保存的第二数据。对于要在第一和第二数据中首先输出的数据，稍后要输出的数据的输出定时被延迟，首先要输出的数据对应于第一输出寄存器，稍后要输出的数据被对应于第二输出寄存器，并且将与第一输出寄存器相对应的第二信号传输路径的传输速率设置为高于与第二输出寄存器对应的第二信号传输路径的传输速率。

4. 发明申请

US20100309706A1 Load reduced memory module and memory system including the same 有权
标题翻译：负载减少的内存模块和包含相同的内存系统
公开(公告)号：US20100309706A1
公开(公告)日：2010-12-09
申请号：US12801326
申请日：2010-06-03
申请人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
发明人： Shunichi Saito , Toshio Sugano , Atsushi Hiraishi , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa
IPC分类号： G11C5/02 , G11C7/00
CPC分类号： G11C7/00 , G11C5/02 , G11C5/04 , G11C5/063 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/109 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/00014
摘要： A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片，多个数据寄存器缓冲器以及安装在模块PCB上的命令/地址/控制寄存器缓冲器。数据寄存器缓冲器与存储器芯片执行数据传输。命令/地址/控制寄存器缓冲器执行命令/地址/控制信号的缓冲并产生控制信号。缓冲的命令/地址/控制信号被提供给存储器芯片，并且控制信号被提供给数据寄存器缓冲器。根据本发明，由于数据寄存器缓冲器和存储器芯片之间的线路长度被缩短，可以实现相当高的数据传输速率。

5. 发明申请

US20090002048A1 Reference voltage generating circuit 有权
标题翻译：参考电压发生电路
公开(公告)号：US20090002048A1
公开(公告)日：2009-01-01
申请号：US12230489
申请日：2008-08-29
申请人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
发明人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
IPC分类号： H03L5/00
CPC分类号： G05F3/30
摘要： Disclosed is a reference voltage generating circuit which includes resistors R0, R0 and R3, a differential amplifier A1 and transistors Q1, Q2 and Q3. The collectors of the transistors Q1 and Q2 are connected to differential input terminals of the differential amplifier, while one ends of the R0, R0 and R3 are connected in common to an output of the differential amplifier A1. The other ends of the two resistors R0 are connected in common to the collectors of the transistors Q1 and Q2, while the other end of the resistor R1 is connected to the collector and the base of the transistor Q3, which transistor Q3 has the base connected to the bases of the transistors Q1 and Q2. The emitter size ratio of the transistors Q1 and Q2 is set to 1:N. A current of a value approximately equal to that of the collector current of the transistor Q1 or Q2 and a current with a positive temperature coefficient larger than the first-stated current are caused to flow through the resistor R1. The reference voltage generating circuit outputs a voltage corresponding to the sum of a voltage generated across both ends of the resistor R1 and a base-to-emitter voltage VBE3 of the transistor Q3.
摘要翻译：公开了一种参考电压产生电路，其包括电阻器R0，R0和R3，差分放大器A1和晶体管Q1，Q2和Q3。晶体管Q1和Q2的集电极连接到差分放大器的差分输入端，而R0，R0和R3的一端共同连接到差分放大器A1的输出端。两个电阻R0的另一端共同连接到晶体管Q1和Q2的集电极，而电阻器R1的另一端连接到晶体管Q3的集电极和基极，晶体管Q3的基极连接到晶体管Q1和Q2的基极。晶体管Q1和Q2的发射极尺寸比设定为1：N。导致大致等于晶体管Q1或Q2的集电极电流的值的电流和大于先前电流的正温度系数的电流流过电阻器R1。参考电压产生电路输出与电阻器R1两端产生的电压和晶体管Q3的基极 - 发射极电压VBE3之和的和相对应的电压。

6. 发明授权

US6088252A Semiconductor storage device with an improved arrangement of electrodes and peripheral circuits to improve operational speed and integration 有权
标题翻译：半导体存储器件具有改进的电极和外围电路的布置，以提高操作速度和集成度
公开(公告)号：US6088252A
公开(公告)日：2000-07-11
申请号：US177889
申请日：1998-10-23
申请人： Hiroki Fujisawa , Masayuki Nakamura
发明人： Hiroki Fujisawa , Masayuki Nakamura
IPC分类号： G11C11/401 , G11C5/02 , G11C8/10 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108
CPC分类号： G11C8/10 , G11C5/025
摘要： A semiconductor storage device is provided in which electrodes are provided so as to be arranged in the central portion so as to divide a semiconductor chip into two segments, an address buffer is provided neighboring those electrodes which receive address signals among said electrodes, memory arrays are constituted so as to be divided into at least two groups sandwiching said central portion, an address decoder is provided on a peripheral side of the semiconductor chip opposite to the central portion where the electrodes of the semiconductor chip are formed, and a predecoder for decoding the address signals is arranged on an intermediate portion extending from said central portion to a portion where said address decoder is provided.
摘要翻译：提供一种半导体存储装置，其中设置电极以便将半导体芯片分成两个部分，将这些电极设置在中心部分中，与在这些电极之间接收地址信号的那些电极相邻设置地址缓冲器，存储器阵列是被构造成被分成夹持所述中心部分的至少两个组，地址解码器设置在半导体芯片的与形成半导体芯片的电极的中心部分相对的周边，以及用于对地址信号被布置在从所述中心部分延伸到提供所述地址解码器的部分的中间部分上。

7. 发明申请

US20100312925A1 Load reduced memory module 审中-公开
标题翻译：减少内存模块
公开(公告)号：US20100312925A1
公开(公告)日：2010-12-09
申请号：US12801327
申请日：2010-06-03
申请人： Fumiyuki Osanai , Toshio Sugano , Atsushi Hiraishi , Shunichi Saito , Masayuki Nakamura , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Toshio Sugano , Atsushi Hiraishi , Shunichi Saito , Masayuki Nakamura , Hiroki Fujisawa
IPC分类号： G06F13/00 , G06F12/00 , G06F3/00
CPC分类号： G11C5/04 , G11C7/1045 , G11C7/1066 , G11C7/1093 , G11C11/4076 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/3011 , H01L2924/00012 , H01L2924/00
摘要： A memory module includes a plurality of data connectors provided along a long side of a module substrate, a plurality of memory chips and a plurality of data register buffers mounted on the module substrate, a data line that connects the data connectors and the data register buffers, and data lines that connect the data register buffers and the memory chips. Each of the data register buffers and a plurality of data connectors and a plurality of memory chips corresponding to the data register buffer are arranged side by side in a direction of a short side of the module substrate. According to the present invention, because each line length of the data lines is considerably shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括沿着模块衬底的长边提供的多个数据连接器，多个存储器芯片和安装在模块衬底上的多个数据寄存器缓冲器，连接数据连接器和数据寄存器缓冲器的数据线以及连接数据寄存器缓冲器和存储器芯片的数据线。每个数据寄存器缓冲器和多个数据连接器以及对应于数据寄存器缓冲器的多个存储器芯片沿着模块基板的短边方向并排布置。根据本发明，由于数据线的每行长度大大缩短，所以可以实现相当高的数据传送速度。

8. 发明申请

US20100312956A1 Load reduced memory module 审中-公开
标题翻译：减少内存模块
公开(公告)号：US20100312956A1
公开(公告)日：2010-12-09
申请号：US12801325
申请日：2010-06-03
申请人： Atsushi Hiraishi , Toshio Sugano , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa , Shunichi Saito
发明人： Atsushi Hiraishi , Toshio Sugano , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa , Shunichi Saito
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G11C5/04 , G11C7/1045 , G11C7/1057 , G11C7/1084 , H01L2224/48091 , H01L2224/48227 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片和安装在模块基板上的多个数据寄存器缓冲器。至少两个存储器芯片被分配给每个数据寄存器缓冲器。每个数据寄存器缓冲器包括通过第一数据线连接到数据连接器的M个输入/输出端子（M是等于或大于1的正整数）和N个输入/输出端子（N是正整数等于大于2M），其经由第二和第三数据线连接到对应的存储器芯片，使得第二和第三数据线的数量是第一数据线的数量的N / M倍。根据本发明，由于第二和第三数据线的负载容量减少了很多，所以可以实现相当高的数据传输速率。

9. 发明授权

US07750726B2 Reference voltage generating circuit 有权
标题翻译：基准电压发生电路
公开(公告)号：US07750726B2
公开(公告)日：2010-07-06
申请号：US12230489
申请日：2008-08-29
申请人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
发明人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
IPC分类号： G05F3/02 , G05F1/10
CPC分类号： G05F3/30
摘要： A reference voltage generating circuit includes a current generating section, a voltage generating section, a voltage dividing circuit, and a synthesis section. The current generating section generates a first current having a positive temperature coefficient. The voltage generating section generates a voltage having a negative temperature coefficient. The voltage dividing circuit divides the voltage of the negative temperature coefficient, generated by the voltage generating section. The synthesis section generates a voltage which is the sum of a terminal voltage obtained on causing the first current through a resistor and a voltage obtained on dividing the voltage having the negative temperature coefficient by the voltage dividing circuit, and outputs the sum voltage generated as a reference voltage.
摘要翻译：参考电压产生电路包括电流产生部分，电压产生部分，分压电路和合成部分。电流产生部分产生具有正温度系数的第一电流。电压产生部分产生具有负温度系数的电压。分压电路分压由电压产生部产生的负温度系数的电压。合成部分产生电压，该电压是通过使通过电阻器的第一电流获得的端电压与通过分压电路分压具有负温度系数的电压获得的电压之和，并输出产生的和电压参考电压。

10. 发明申请

US20070132506A1 Reference voltage generating circuit 有权
标题翻译：参考电压发生电路
公开(公告)号：US20070132506A1
公开(公告)日：2007-06-14
申请号：US11603121
申请日：2006-11-22
申请人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
发明人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： Disclosed is a reference voltage generating circuit which includes resistors R0, R0 and R3, a differential amplifier A1 and transistors Q1, Q2 and Q3. The collectors of the transistors Q1 and Q2 are connected to differential input terminals of the differential amplifier, while one ends of the R0, R0 and R3 are connected in common to an output of the differential amplifier A1. The other ends of the two resistors R0 are connected in common to the collectors of the transistors Q1 and Q2, while the other end of the resistor R1 is connected to the collector and the base of the transistor Q3, which transistor Q3 has the base connected to the bases of the transistors Q1 and Q2. The emitter size ratio of the transistors Q1 and Q2 is set to 1:N. A current of a value approximately equal to that of the collector current of the transistor Q1 or Q2 and a current with a positive temperature coefficient larger than the first-stated current are caused to flow through the resistor R1. The reference voltage generating circuit outputs a voltage corresponding to the sum of a voltage generated across both ends of the resistor R1 and a base-to-emitter voltage VBE3 of the transistor Q3.
摘要翻译：公开了一种参考电压发生电路，其包括电阻器R 0，R 0和R 3，差分放大器A 1和晶体管Q 1，Q 2和Q 3。晶体管Q 1和Q 2的集电极连接到差分放大器的差分输入端，而R 0，R 0和R 3的一端共同连接到差分放大器A 1的输出端。两个电阻R 0的另一端共同连接到晶体管Q 1和Q 2的集电极，而电阻器R 1的另一端连接到晶体管Q 3的集电极和基极，该晶体管Q 3 Q 3的基极连接到晶体管Q 1和Q 2的基极。晶体管Q 1和Q 2的发射极尺寸比被设定为1：N。导致大致等于晶体管Q 1或Q 2的集电极电流的值的电流和具有大于第一电流的正温度系数的电流流过电阻器R 1。参考电压产生电路输出与电阻器R 1的两端产生的电压和晶体管Q 3的基极 - 发射极电压V BE3 / N之和的和相对应的电压。

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