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91. 发明申请

US20120002476A1 Semiconductor Memory With Improved Block Switching 有权
标题翻译：半导体存储器改进块切换
公开(公告)号：US20120002476A1
公开(公告)日：2012-01-05
申请号：US13233602
申请日：2011-09-15
申请人： Thomas Yan , Luca Fasoli , Roy E. Scheuerlein
发明人： Thomas Yan , Luca Fasoli , Roy E. Scheuerlein
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C7/18 , G11C13/004 , G11C16/24 , G11C2029/0411 , G11C2213/71 , G11C2213/72
摘要： A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.
摘要翻译：非易失性存储器核心包括一个或多个存储器空间。每个存储器托架包括一个或多个存储器块，其包括非易失性存储元件的分组。在一个实施例中，特定存储器架中的存储器块共享一组读/写电路。在存储器操作期间，存储器块被转换为活动状态和非活动状态。将块从非活动状态转换到活动状态的过程包括使得进入活动状态的存储块与先前处于活动状态的另一个存储块之间的电荷共享成为可能。这种电荷共享提高了存储器系统的性能和/或降低了能量消耗。

92. 发明申请

US20110235405A1 PROGRAMMING NON-VOLATILE STORAGE ELEMENT USING CURRENT FROM OTHER ELEMENT 有权
标题翻译：使用其他元素的电流编程非易失性存储元件
公开(公告)号：US20110235405A1
公开(公告)日：2011-09-29
申请号：US13154832
申请日：2011-06-07
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A non-volatile storage apparatus includes a set of Y lines, a common X line, multiple storage elements each of which is connected to the common X line, and control circuitry in communication with the common X line and the set of Y lines. The multiple data storage elements are capable of being in a first state or a second state. The control circuitry provides control signals to the common X line and the set of Y lines to change a first data storage element of the multiple data storage elements from the first state to the second state by passing a current into the first data storage element from a different Y line through a different storage element. The control circuitry provides control signals to the common X line and the set of Y lines to sequentially change additional data storage elements of the multiple data storage elements from the first state to the second state by passing currents into the additional data storage elements from data storage elements of the multiple data storage elements that were previously changed to the second state and their associated different Y lines.
摘要翻译：非易失性存储装置包括一组Y线，公共X线，多个存储元件，每个存储元件连接到公共X线，以及与公共X线和Y线组通信的控制电路。多个数据存储元件能够处于第一状态或第二状态。控制电路向公共X线和Y线组提供控制信号，以将多个数据存储元件的第一数据存储元件从第一状态改变到第二状态，通过将电流从第一数据存储元件不同的Y线通过不同的存储元件。控制电路向公共X线路和Y线组提供控制信号，以通过将电流从数据存储器传递到附加数据存储元件中来顺序地将多个数据存储元件的附加数据存储元件从第一状态改变到第二状态先前更改为第二状态的多个数据存储元素的元素及其相关的不同Y行。

93. 发明申请

US20110235404A1 PULSE RESET FOR NON-VOLATILE STORAGE 有权
标题翻译：非易失性存储器的脉冲复位
公开(公告)号：US20110235404A1
公开(公告)日：2011-09-29
申请号：US13154795
申请日：2011-06-07
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C7/12 , G11C7/22 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/32 , G11C2213/34 , G11C2213/71
摘要： A non-volatile storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits to SET and RESET the resistance-switching elements. The circuits that RESET the resistance-switching elements provide a pulse to the memory cells that is large enough in magnitude to SET and RESET the memory cells, and long enough to potentially RESET the memory cell but not long enough to SET the memory cells.
摘要翻译：非易失性存储系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储单元的三维存储器阵列（衬底上方），以及用于设置和复位电阻切换元素。复位电阻切换元件的电路向存储器单元提供足够大的脉冲以设置和复位存储器单元，并且足够长以潜在地重置存储器单元，但不足以设置存储器单元。

94. 发明授权

US08014185B2 Multiple series passive element matrix cell for three-dimensional arrays 有权
标题翻译：用于三维阵列的多系列无源元矩阵单元
公开(公告)号：US08014185B2
公开(公告)日：2011-09-06
申请号：US12216677
申请日：2008-07-09
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C17/00
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/025 , G11C2213/16 , G11C2213/35 , G11C2213/72 , G11C2213/74 , H01L27/2409 , H01L27/2418 , H01L45/04 , H01L45/1233 , H01L45/149
摘要： A nonvolatile memory cell including at least two two-terminal non-linear steering elements arranged in series, and a resistivity switching storage element arranged in series with the at least two two-terminal non-linear steering elements. A memory array, comprising a plurality of the nonvolatile memory cells is also described. A method of forming a nonvolatile memory cell is also described.
摘要翻译：包括串联布置的至少两个两端非线性转向元件的非易失性存储单元和与所述至少两个两端非线性转向元件串联布置的电阻率切换存储元件。还描述了包括多个非易失性存储器单元的存储器阵列。还描述了形成非易失性存储单元的方法。

95. 发明授权

US07935553B2 Method for fabricating high density pillar structures by double patterning using positive photoresist 有权
标题翻译：通过使用正性光致抗蚀剂的双重图案制造高密度柱结构的方法
公开(公告)号：US07935553B2
公开(公告)日：2011-05-03
申请号：US12777046
申请日：2010-05-10
申请人： Roy E. Scheuerlein , Steven Radigan
发明人： Roy E. Scheuerlein , Steven Radigan
IPC分类号： H01L21/00
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain, and removing the second photoresist pattern.
摘要翻译：制造半导体器件的方法包括在下层上形成第一光致抗蚀剂层，将第一光致抗蚀剂层图案化为第一光致抗蚀剂图案，其中第一光致抗蚀剂图案包括位于下层之上的多个间隔开的第一光致抗蚀剂特征，以及使用第一光致抗蚀剂图案作为掩模蚀刻下层，以形成多个第一间隔的特征。该方法还包括去除第一光致抗蚀剂图案，在多个第一间隔开的特征上形成第二光致抗蚀剂层，以及将第二光致抗蚀剂层图案化为第二光致抗蚀剂图案，其中第二光致抗蚀剂图案包括覆盖边缘多个第一间隔开的特征部分。该方法还包括使用第二光致抗蚀剂图案作为掩模蚀刻多个第一间隔开的特征的暴露部分，使得多个第一间隔开的特征中的多个间隔开的边缘部分保留，并且去除第二光致抗蚀剂图案。

96. 发明申请

US20110095434A1 APPARATUS AND METHODS OF FORMING MEMORY LINES AND STRUCTURES USING DOUBLE SIDEWALL PATTERNING FOR FOUR TIMES HALF PITCH RELIEF PATTERNING 有权
标题翻译：使用双重格式化方式形成记忆线和结构的四种方法的设备和方法
公开(公告)号：US20110095434A1
公开(公告)日：2011-04-28
申请号：US12911887
申请日：2010-10-26
申请人： Roy E. Scheuerlein , Yoichiro Tanaka
发明人： Roy E. Scheuerlein , Yoichiro Tanaka
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
摘要翻译：本发明提供用于制造使用双重侧壁图案化四次半间距浮雕图案化的存储器线和结构的装置，方法和系统。本发明包括从设置在基板上方的第一模板层形成特征，形成邻近特征的半间距侧壁间隔，通过使用半间距侧壁间隔物作为硬掩模在第二模板层中形成更小的特征，形成四分之一间距侧壁靠近较小特征的间隔物，并且通过使用四分之一间距侧壁间隔物作为硬掩模，从导体层形成导体特征。公开了许多附加方面。

97. 发明申请

US20110075468A1 REVERSE SET WITH CURRENT LIMIT FOR NON-VOLATILE STORAGE 有权
标题翻译：随着非易失性存储的电流限制反向设置
公开(公告)号：US20110075468A1
公开(公告)日：2011-03-31
申请号：US12963540
申请日：2010-12-08
申请人： Roy E. Scheuerlein , Tianhong Yan
发明人： Roy E. Scheuerlein , Tianhong Yan
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3481 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion.
摘要翻译：存储系统包括衬底，衬底上的控制电路，包括多个可逆电阻开关元件的三维存储器阵列（衬底上方），以及用于限制可逆电阻切换元件的SET电流的电路。存储器单元以反向偏置的方式被设置。

98. 发明申请

US20110051506A1 FLEXIBLE MULTI-PULSE SET OPERATION FOR PHASE-CHANGE MEMORIES 有权
标题翻译：用于相变记忆的灵活多脉冲设置操作
公开(公告)号：US20110051506A1
公开(公告)日：2011-03-03
申请号：US12551553
申请日：2009-08-31
申请人： Tyler Thorp , Roy E. Scheuerlein
发明人： Tyler Thorp , Roy E. Scheuerlein
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2013/0092
摘要： Methods and apparatus are provided that include reading a plurality of sets of program pulse tuning instructions from a memory page, the memory page including a plurality of memory cells; and creating a plurality of program pulses in accordance with the plurality of sets of program pulses to program the plurality of memory cells. The plurality of sets of program pulse tuning instructions may be different from one another in at least one respect.
摘要翻译：提供了包括从存储器页面读取多组编程脉冲调整指令的方法和装置，所述存储器页面包括多个存储器单元; 以及根据所述多组编程脉冲创建多个编程脉冲，以对所述多个存储单元进行编程。多组编程脉冲调谐指令在至少一个方面可以彼此不同。

99. 发明授权

US07887999B2 Method of making a pillar pattern using triple or quadruple exposure 有权
标题翻译：使用三重或四重曝光制作柱状图案的方法
公开(公告)号：US07887999B2
公开(公告)日：2011-02-15
申请号：US12005276
申请日：2007-12-27
申请人： Roy E. Scheuerlein , Christopher J. Petti
发明人： Roy E. Scheuerlein , Christopher J. Petti
IPC分类号： G03F7/22 , H01L21/02
CPC分类号： H01L21/32139 , G03F1/70 , G03F7/203 , H01L21/0274 , H01L21/31144 , H01L27/0688 , H01L27/1021 , Y10S430/153
摘要： Methods of making pillar shaped device array using a triple or quadruple exposure technique are described. A plurality of pillar shaped devices are formed arranged in a hexagonal or rectangular pattern.
摘要翻译：描述使用三重或四重曝光技术制造柱形装置阵列的方法。多个柱状装置形成为六边形或矩形图案。

100. 发明申请

US20100290301A1 MEMORY ARRAY INCORPORATING NOISE DETECTION LINE 有权
标题翻译：存储器阵列噪声检测线
公开(公告)号：US20100290301A1
公开(公告)日：2010-11-18
申请号：US12847378
申请日：2010-07-30
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C5/025 , G11C7/067 , G11C7/18 , G11C8/08 , G11C8/10 , G11C17/18 , G11C2207/063
摘要： A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.
摘要翻译：存储器阵列包括用于感测位线电流的感测电路，同时保持所选位线的电压基本上不变。字线和位线被偏置，使得基本上不会在半选择的存储器单元上施加偏置电压，这几乎消除了通过半选择的存储器单元的泄漏电流。感测的位线电流很大程度上仅来自所选存储单元的电流。存储器阵列中的噪声检测线减少了从未选择的字线耦合到所选位线的影响。在优选实施例中，具有在多于一个层上形成位线的多个轨道堆叠的三维存储器阵列包括与每个位线层相关联的至少一个噪声检测线。感测电路连接到选定的位线及其相关的噪声检测线。

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