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91. 发明申请

US20100029082A1 METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION 有权
标题翻译：用于高密度等离子体化学蒸气沉积的方法和装置
公开(公告)号：US20100029082A1
公开(公告)日：2010-02-04
申请号：US12185339
申请日：2008-08-04
申请人： Daewon Yang , Kangguo Cheng , Pavel Smetana , Richard S. Wise , Keith Kwong Hon Wong
发明人： Daewon Yang , Kangguo Cheng , Pavel Smetana , Richard S. Wise , Keith Kwong Hon Wong
IPC分类号： H01L21/311 , C23C16/00
CPC分类号： C23C16/507 , C23C16/345 , C23C16/402 , C23C16/45578 , C23C16/4586 , C23C16/56 , H01J37/20 , H01J37/321 , H01J2237/20207 , H01J2237/3323 , H01L21/31608 , H01L21/3185 , H01L27/10867
摘要： Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.
摘要翻译：通过形成多个STI沟槽与FET结合形成浅沟槽电容器; 对于FET，在第一和第二STI沟槽之间注入具有第一极性的第一单元阱; 对于电容器，在第三个STI沟槽的区域中注入具有第二极性的第二单元阱; 从第三STI沟槽去除电介质材料; 形成具有位于所述STI沟槽的所述第一和第二STI沟槽之间的第一部分和位于所述第三沟槽中并延伸到所述第三沟槽中的第二部分的栅极堆叠; 并且执行与第二单元阱相同极性的源极/漏极注入，从而在第一单元阱中形成FET，以及在第二单元阱中形成电容器。第二极性可以与第一极性相反。额外的植入物可以减少第二细胞中的ESR。

92. 发明申请

US20100001253A1 Method for delineation of phase change memory cell via film resistivity modification 有权
标题翻译：通过膜电阻率修饰来描绘相变记忆单元的方法
公开(公告)号：US20100001253A1
公开(公告)日：2010-01-07
申请号：US12492618
申请日：2009-06-26
申请人： John Christopher Arnold , Lawrence Alfred Clevenger , Timothy Joseph Dalton , Michael Christopher Gaidis , Louis L. Hsu , Carl John Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： John Christopher Arnold , Lawrence Alfred Clevenger , Timothy Joseph Dalton , Michael Christopher Gaidis , Louis L. Hsu , Carl John Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the phase change element thereby reducing the contact area between the phase change element and the first electrode and thereby increasing the current density through the phase change element and effectively inducing the phase change at lower levels of current and reduced programming power.
摘要翻译： PCM单元结构包括第一电极，相变元件和第二电极，其中相变元件插入在第一电极和第二电极之间，并且仅第一电极的周边边缘与相变元件接触，减少相变元件与第一电极之间的接触面积，从而增加通过相变元件的电流密度，并有效地在较低的电流电平和降低的编程功率下引起相变。

93. 发明授权

US07635884B2 Method and structure for forming slot via bitline for MRAM devices 有权
标题翻译：用于通过MRAM器件的位线形成槽的方法和结构
公开(公告)号：US07635884B2
公开(公告)日：2009-12-22
申请号：US11193660
申请日：2005-07-29
申请人： Michael C. Gaidis , Carl Radens , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Carl Radens , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/94
CPC分类号： B82Y10/00 , H01L27/222 , H01L43/12
摘要： A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.
摘要翻译：磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。

94. 发明授权

US07557424B2 Reversible electric fuse and antifuse structures for semiconductor devices 有权
标题翻译：用于半导体器件的可逆电熔丝和反熔丝结构
公开(公告)号：US07557424B2
公开(公告)日：2009-07-07
申请号：US11619264
申请日：2007-01-03
申请人： Keith Kwong Hon Wong , Chih-Chao Yang , Haining S Yang
发明人： Keith Kwong Hon Wong , Chih-Chao Yang , Haining S Yang
IPC分类号： H01L23/58
CPC分类号： H01L23/5256 , H01L23/5252 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of fabricating reversible fuse and antifuse structures for semiconductor devices is provided. In one embodiment, the method includes forming at least one line having a via opening for exposing a portion of a plurality of interconnect features; conformally depositing a first material layer over the via opening; depositing a second material layer over the first material layer, wherein the depositing overhangs a portion of the second material layer on a top portion of the via opening; and depositing a blanket layer of insulating material, where the depositing forms a plurality of fuse elements each having an airgap between the insulating material and the second material layer. The method further includes forming a plurality of electroplates in the insulator material connecting the fuse elements. In another embodiment, the method includes depositing a first and a second material layer on a semiconductor substrate, wherein the second material layer having a higher electrical conductivity than the first material layer; selectively etching the first and second material layer to create at least one constricted region to facilitate electromigration of the second material; wherein the electromigration creates a plurality of micro voids; and forming a plurality of electrical contacts on the second material layer.
摘要翻译：提供一种用于制造用于半导体器件的可逆熔丝和反熔丝结构的结构和方法。在一个实施例中，该方法包括形成至少一条线，其具有用于暴露多个互连特征的一部分的通孔; 在通孔开口上共形沉积第一材料层; 在所述第一材料层上沉积第二材料层，其中所述沉积在所述通孔开口的顶部部分上突出所述第二材料层的一部分; 以及沉积绝缘材料的覆盖层，其中所述沉积形成多个熔丝元件，每个熔丝元件在所述绝缘材料和所述第二材料层之间具有气隙。该方法还包括在连接熔丝元件的绝缘体材料中形成多个电镀层。在另一个实施例中，该方法包括在半导体衬底上沉积第一和第二材料层，其中第二材料层具有比第一材料层更高的导电性; 选择性地蚀刻第一和第二材料层以产生至少一个收缩区域以促进第二材料的电迁移; 其中所述电迁移产生多个微空隙; 以及在所述第二材料层上形成多个电接触。

95. 发明申请

US20090152651A1 GATE STACK STRUCTURE WITH OXYGEN GETTERING LAYER 审中-公开
标题翻译：具有氧气捕获层的门盖结构
公开(公告)号：US20090152651A1
公开(公告)日：2009-06-18
申请号：US11958595
申请日：2007-12-18
申请人： Huiming Bu , Rick Carter , Michael P. Chudzik , Troy L. Graves , Michael A. Gribelyuk , Rashmi Jha , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Hongwen Yan , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Huiming Bu , Rick Carter , Michael P. Chudzik , Troy L. Graves , Michael A. Gribelyuk , Rashmi Jha , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Hongwen Yan , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L29/78
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517
摘要： A transistor has a channel region in a substrate and source and drain regions in the substrate on opposite sides of the channel region. A gate stack is formed on the substrate above the channel region. This gate stack comprises an interface layer contacting the channel region of the substrate, and a high-k dielectric layer (having a dielectric constant above 4.0) contacting (on) the interface layer. A Nitrogen rich first metal Nitride layer contacts (is on) the dielectric layer, and a metal rich second metal Nitride layer contacts (is on) the first metal Nitride layer. Finally, a Polysilicon cap contacts (is on) the second metal Nitride layer.
摘要翻译：晶体管在衬底中具有通道区域，在沟道区域的相对侧上具有衬底中的源极和漏极区域。栅极堆叠形成在沟道区域上方的衬底上。该栅极堆叠包括与衬底的沟道区域接触的界面层和与界面层（上）接触的高k电介质层（介电常数高于4.0）。富氮的第一金属氮化物层在电介质层上接触，并且富金属的第二金属氮化物层与第一金属氮化物层接触（在）上。最后，多晶硅帽与第二金属氮化物层接触（在）上。

96. 发明授权

US07544608B2 Porous and dense hybrid interconnect structure and method of manufacture 失效
标题翻译：多孔密集混合互连结构及制造方法
公开(公告)号：US07544608B2
公开(公告)日：2009-06-09
申请号：US11458464
申请日：2006-07-19
申请人： Chih-Chao Yang , Keith Kwong Hon Wong , Haining Yang
发明人： Chih-Chao Yang , Keith Kwong Hon Wong , Haining Yang
IPC分类号： H01L21/00
CPC分类号： H01L23/53295 , H01L21/7682 , H01L21/76835 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing a structure includes depositing a dense dielectric over the entire wafer, which includes areas that require low dielectric capacitance and areas that require high mechanical strength. The method further includes masking areas of the dense dielectric over the areas that require high mechanical strength and curing unmasked areas of the dense dielectric to burn out porogens inside the dense dielectric and transform the unmasked areas of the dense dielectric to porous dielectric material. A semiconductor structure comprises porous and dense hybrid interconnects for high performance and reliability semiconductor applications.
摘要翻译：一种用于制造结构的方法包括在整个晶片上沉积致密电介质，其包括需要低介电电容的区域和需要高机械强度的区域。该方法还包括在需要高机械强度的区域和致密电介质的固化未掩蔽区域的区域上掩蔽致密电介质的区域，以烧尽致密电介质内的致孔剂，并将致密电介质的未掩模区域转化为多孔电介质材料。半导体结构包括用于高性能和可靠性半导体应用的多孔和致密的混合互连。

97. 发明授权

US07531407B2 Semiconductor integrated circuit devices having high-Q wafer backside inductors and methods of fabricating same 失效
标题翻译：具有高Q晶片背面电感器的半导体集成电路器件及其制造方法
公开(公告)号：US07531407B2
公开(公告)日：2009-05-12
申请号：US11488242
申请日：2006-07-18
申请人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence Clevenger , Timothy Joseph Dalton , Louis Hsu , Carl Radens , Vidhya Ramachandran , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/8234
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip inductors formed on the chip backside and connected to integrated circuits on the chip frontside using through-wafer interconnects. For example, a semiconductor device with a backside integrated inductor includes a semiconductor substrate having a frontside, a backside and a buried insulating layer interposed between the front and backsides of the substrate. An integrated circuit is formed on the frontside of the semiconductor substrate and an integrated inductor is formed on the backside of the semiconductor substrate. An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit. The semiconductor substrate may be an SOI (silicon on insulator) structure.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面上的高Q片上电感器，并且使用晶片间互连连接到芯片前端的集成电路。例如，具有背面集成电感器的半导体器件包括半导体衬底，其具有插入在衬底的前侧和后侧之间的前侧，后侧和掩埋绝缘层。在半导体衬底的前侧形成集成电路，在半导体衬底的背面形成集成电感器。通过埋层绝缘层形成互连结构，将集成电感器连接到集成电路。半导体衬底可以是SOI（绝缘体上硅）结构。

98. 发明申请

US20080293257A1 DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE 失效
标题翻译：双层封装层互连结构
公开(公告)号：US20080293257A1
公开(公告)日：2008-11-27
申请号：US12186923
申请日：2008-08-06
申请人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Haining Yang , Keith Kwong Hon Wong
IPC分类号： H01L21/768
CPC分类号： H01L21/76829 , H01L21/76834 , Y10S438/927
摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.
摘要翻译： Cu互连上的高拉伸应力覆盖层，以减少Cu /介电界面处的铜迁移和原子排空。高拉伸电介质膜通过沉积多层薄的电介质材料形成，每个层的厚度在约50埃以下。每个电介质层在沉积每个后续介电层之前进行等离子体处理，使得电介质盖具有内部拉伸应力。

99. 发明申请

US20080239785A1 HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS 有权
标题翻译：高密度平面磁畴壁记忆装置
公开(公告)号：US20080239785A1
公开(公告)日：2008-10-02
申请号：US12136089
申请日：2008-06-10
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： G11C19/02
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure.
摘要翻译：具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括其中具有收缩部的写入线，所述收缩部位于与相关联的移位寄存器结构中的所述多个不连续点的位置对应的点处。

100. 发明申请

US20080217747A1 INTRODUCTION OF METAL IMPURITY TO CHANGE WORKFUNCTION OF CONDUCTIVE ELECTRODES 有权
标题翻译：介绍金属污染物改变导电电极的功能
公开(公告)号：US20080217747A1
公开(公告)日：2008-09-11
申请号：US12125508
申请日：2008-05-22
申请人： Michael P. Chudzik , Bruce B. Doris , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri , Yun Y. Wang , Keith Kwong Hon Wong
发明人： Michael P. Chudzik , Bruce B. Doris , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri , Yun Y. Wang , Keith Kwong Hon Wong
IPC分类号： H01L23/58 , H01L21/469
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823828 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.
摘要翻译：提供半导体结构，例如场效应晶体管（FET）和/或金属氧化物半导体电容器（MOSCAP），其中通过将金属杂质引入到含金属的物质中来改变导电电极堆叠的功函数材料层与导电电极一起存在于电极堆叠中。金属杂质的选择取决于电极是否具有n型功函数或p型功函数。本发明还提供一种制造这种半导体结构的方法。金属杂质的引入可以通过共沉积含有金属的材料和改变金属杂质的功函数的层来形成，形成其中金属杂质层存在于含金属材料的层之间的叠层，或通过形成包括在含金属材料上方和/或下面的金属杂质的材料层，然后加热该结构，使得金属杂质被引入到含金属的材料中。

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