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91. 发明授权

US06448629B2 Semiconductor device and method of making same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06448629B2
公开(公告)日：2002-09-10
申请号：US09354742
申请日：1999-07-29
申请人： Rebecca D. Mih , Kevin S. Petrarca
发明人： Rebecca D. Mih , Kevin S. Petrarca
IPC分类号： H01L2906
CPC分类号： H01L21/0332 , H01L21/76224 , H01L21/7684
摘要： A second or cap dielectric layer is interposed between the usual or base dielectric layer and the metallic circuitry layer of a semiconductor device. The base dielectric layer has a plurality of recesses in an inactive part of the semiconductor device into which parts of the cap dielectric layer extend to interlock the cap dielectric layer to the base dielectric layer and to oppose shearing or tearing of the either (1) the metallic circuitry layer as the metallic circuitry layer is subjected to chemical-mechanical polishing, or (2) a hard mask layer from the base dielectric layer as the metallic circuitry layer is subjected to chemical-mechanical polishing.
摘要翻译：第二或盖电介质层介于通常的或基底电介质层与半导体器件的金属电路层之间。基极电介质层在半导体器件的非活性部分中具有多个凹部，盖电介质层的部分延伸以将盖电介质层与基底电介质层互锁，并且相对于（1）的剪切或撕裂金属电路层作为金属电路层进行化学机械抛光，或（2）当金属电路层进行化学机械抛光时，从基极介电层获得硬掩模层。

92. 发明授权

US08999764B2 Ionizing radiation blocking in IC chip to reduce soft errors 有权
标题翻译： IC芯片中的电离辐射阻断减少软错误
公开(公告)号：US08999764B2
公开(公告)日：2015-04-07
申请号：US11836819
申请日：2007-08-10
申请人： Mukta G. Farooq , Ian D. Melville , Kevin S. Petrarca , Kenneth P. Rodbell
发明人： Mukta G. Farooq , Ian D. Melville , Kevin S. Petrarca , Kenneth P. Rodbell
IPC分类号： H01L21/00 , H01L23/532 , H01L23/556
CPC分类号： H01L23/5329 , H01L23/556 , H01L2924/0002 , Y10S438/958 , Y10S438/967 , H01L2924/00
摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
摘要翻译：公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。

93. 发明授权

US08802990B2 Self-aligned nano-scale device with parallel plate electrodes 有权
标题翻译：具有平行平板电极的自对准纳米级装置
公开(公告)号：US08802990B2
公开(公告)日：2014-08-12
申请号：US13432037
申请日：2012-03-28
申请人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
IPC分类号： H01B5/14 , H01L21/76 , H01L21/764
CPC分类号： B81C1/00698 , B81B2201/0292
摘要： A contiguous deep trench includes a first trench portion having a constant width between a pair of first parallel sidewalls, second and third trench portions each having a greater width than the first trench portion and laterally connected to the first trench portion. A non-conformal deposition process is employed to form a conductive layer that has a tapered geometry within the contiguous deep trench portion such that the conductive layer is not present on bottom surfaces of the contiguous deep trench. A gap fill layer is formed to plug the space in the first trench portion. The conductive layer is patterned into two conductive plates each having a tapered vertical portion within the first trench portion. After removing remaining portions of the gap fill layer, a device is formed that has a small separation distance between the tapered vertical portions of the conductive plates.
摘要翻译：连续的深沟槽包括在一对第一平行侧壁之间具有恒定宽度的第一沟槽部分，第二沟槽部分和第三沟槽部分各自具有比第一沟槽部分更大的宽度并横向连接到第一沟槽部分。使用非共形沉积工艺来形成导电层，该导电层在邻接的深沟槽部分内具有锥形几何形状，使得导电层不存在于邻接的深沟槽的底表面上。形成间隙填充层以堵塞第一沟槽部分中的空间。将导电层图案化为在第一沟槽部分内具有锥形垂直部分的两个导电板。在去除间隙填充层的剩余部分之后，形成在导电板的锥形垂直部分之间具有小间隔距离的装置。

94. 发明授权

US08692649B2 Asset management infrastructure 有权
标题翻译：资产管理基础设施
公开(公告)号：US08692649B2
公开(公告)日：2014-04-08
申请号：US13296242
申请日：2011-11-15
申请人： Lawrence A. Clevenger , Rainer K. Krause , Kevin S. Petrarca , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Rainer K. Krause , Kevin S. Petrarca , Carl J. Radens , Brian C. Sapp
IPC分类号： H04Q9/00
CPC分类号： G08B13/14 , G06Q10/087
摘要： Asset management for control of electric appliances comprises a keycode unit and an equipment unit embedded in an appliance. The keycode unit is located in a protected environment and relates to an asset management area. The equipment unit may store an appliance identification code. The keycode unit and the equipment unit may be in communication contact, whereby the equipment unit sends positioning coordinates to the keycode unit, and wherein the equipment unit is adapted to lock the appliance via the lock unit, in response to a lock signal that the equipment unit receives from the keycode unit, if the appliance moves outside the asset management area.
摘要翻译：用于控制电器的资产管理包括密码单元和嵌入在器具中的设备单元。键码单元位于受保护的环境中，与资产管理区域有关。设备单元可以存储设备标识码。键码单元和设备单元可以是通信接触的，由此设备单元向键码单元发送定位坐标，并且其中设备单元适于经由锁定单元锁定设备，响应于锁定信号，设备如果设备移动到资产管理区域外，则单元从密钥单元接收。

95. 发明授权

US08486751B2 Method of manufacturing a photovoltaic cell 有权
标题翻译：光伏电池的制造方法
公开(公告)号：US08486751B2
公开(公告)日：2013-07-16
申请号：US12952465
申请日：2010-11-23
申请人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Brian C. Sapp
发明人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Brian C. Sapp
IPC分类号： H01L21/00 , H01L21/66
CPC分类号： H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method of manufacturing a photovoltaic cell using a semiconductor wafer having a front side and a rear side, wherein the photovoltaic cell produces electricity when the front side of the semiconductor wafer is illuminated.
摘要翻译：使用具有前侧和后侧的半导体晶片制造光伏电池的方法，其中当半导体晶片的前侧被照亮时，光伏电池产生电力。

96. 发明申请

US20130168395A1 SELF-LOCKING CONTAINER 有权
标题翻译：自锁式容器
公开(公告)号：US20130168395A1
公开(公告)日：2013-07-04
申请号：US13340776
申请日：2011-12-30
申请人： Ira L. Allen , Lawrence A. Clevenger , Kevin S. Petrarca , Carl J. Radens
发明人： Ira L. Allen , Lawrence A. Clevenger , Kevin S. Petrarca , Carl J. Radens
IPC分类号： B65D55/02 , B65D41/04
CPC分类号： B65D79/02 , A61J1/03 , A61J2200/72 , B65D41/04 , B65D55/10 , B65D2213/00
摘要： Method and apparatus to provide a self-locking container to prevent unwanted access to materials stored in the container as a result of exposure to conditions that compromise the effectiveness or safety of the materials. A container may be threaded to receive a threaded lid, and the container may comprise a bolt movable within a channel from a retracted position, which allows the lid to be threadably connected or removed, to a locked position, which prevents removal of the lid. The bolt is movable to the locked position by a drive member, such as a bimetallic strip or a shape-memory element that drive the bolt in response to exposure to the condition that compromises the material.
摘要翻译：提供自锁容器的方法和装置，以防止由于暴露于损害材料的有效性或安全性的条件而导致存储在容器中的材料的不期望的访问。容器可以是螺纹以接收带螺纹的盖子，并且容器可以包括螺栓，该螺栓可在通道内从缩回位置移动，该缩回位置允许盖子被螺纹连接或移除到锁定位置，从而防止盖子移除。螺栓通过驱动构件（例如双金属条或形状记忆元件）可移动到锁定位置，该双金属条或形状记忆元件响应于暴露于损害材料的状况而驱动螺栓。

97. 发明授权

US08439728B2 Reticle carrier 失效
标题翻译：标线载体
公开(公告)号：US08439728B2
公开(公告)日：2013-05-14
申请号：US13278571
申请日：2011-10-21
申请人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
发明人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
IPC分类号： B24B41/06
CPC分类号： G03F1/00 , G03F1/26 , G03F1/50
摘要： A reticle carrier for a polishing tool capable of accommodating a reticle includes a base plate with an obverse and reverse surfaces, a retaining ring secured to the obverse surface of the base plate forming a recess defined by the obverse surface of the rigid base plate and internal edges of the retaining ring. A reticle pad supports a reticle in the recess. The base plate and the reticle pad having an array of matching, aligned passageway holes therethrough for exhaustion of air from space between the base plate and a the reticle and for supply of air to that space so a vacuum can retain a the reticle in place on the reticle carrier under vacuum conditions and application of air under pressure can eject a reticle from the reticle carrier.
摘要翻译：用于能够容纳标线的抛光工具的掩模版载体包括具有正面和反面的基板，固定在基板的正面的保持环，形成由刚性基板的正面限定的凹部和内部固定环的边缘。掩模垫在凹槽中支撑掩模版。基板和标线垫具有一组匹配的对准的通孔，用于从底板和标线板之间的空间排出空气，并将空气供给到该空间，因此真空可以将该掩模版保持在适当的位置上在真空条件下的掩模版载体和在压力下施加空气可以从掩模版载体喷出掩模版。

98. 发明授权

US08367544B2 Self-aligned patterned etch stop layers for semiconductor devices 失效
标题翻译：用于半导体器件的自对准图案蚀刻停止层
公开(公告)号：US08367544B2
公开(公告)日：2013-02-05
申请号：US12582137
申请日：2009-10-20
申请人： Kangguo Cheng , Lawrence A. Clevenger , Johnathan E. Faltermeier , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca
发明人： Kangguo Cheng , Lawrence A. Clevenger , Johnathan E. Faltermeier , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca
IPC分类号： H01L21/44
CPC分类号： H01L21/76808 , H01L21/76802 , H01L21/7681 , H01L21/76825 , H01L21/76829
摘要： A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.
摘要翻译：形成半导体器件的方法包括：图案化在待蚀刻的均匀半导体器件层上形成的光致抗蚀剂层; 对半导体器件进行注入工艺，该注入工艺根据待均匀半导体器件层内待蚀刻的特征的位置以及在要蚀刻的特征的期望深度选择性地埋入自对准的牺牲蚀刻停止层; 将由图案化的光致抗蚀剂层限定的特征图案蚀刻成均匀的半导体器件层，停止在注入的牺牲蚀刻停止层上; 以及在用填充材料填充蚀刻的特征图案之前去除注入的牺牲蚀刻停止层的剩余部分。

99. 发明授权

US08236655B2 Fuse link structures using film stress for programming and methods of manufacture 有权
标题翻译：使用膜应力的熔断器连接结构进行编程和制造方法
公开(公告)号：US08236655B2
公开(公告)日：2012-08-07
申请号：US12939538
申请日：2010-11-04
申请人： Karl W. Barth , Jeffrey P. Gambino , Tom C. Lee , Kevin S. Petrarca
发明人： Karl W. Barth , Jeffrey P. Gambino , Tom C. Lee , Kevin S. Petrarca
IPC分类号： H01L21/336
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.
摘要翻译：形成可编程熔丝结构的方法包括在衬底中形成至少一个浅沟槽隔离（STI），在至少一个STI上形成e-熔丝，并在该电熔丝上沉积层间电介质（ILD）层。另外，该方法包括移除电子熔丝下的至少一个STI的至少一部分以在e熔丝的一部分下方提供空气间隙，并将e-fuse上的ILD层的至少一部分移除到在电子熔断器的部分上方提供气隙。

100. 发明申请

US20120189767A1 SELF-ALIGNED NANO-SCALE DEVICE WITH PARALLEL PLATE ELECTRODES 有权
标题翻译：具有平行平板电极的自对准纳米尺度装置
公开(公告)号：US20120189767A1
公开(公告)日：2012-07-26
申请号：US13432037
申请日：2012-03-28
申请人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Zhengwen Li , Kevin S. Petrarca , Roger A. Quon , Carl J. Radens , Brian C. Sapp
IPC分类号： B05D5/12 , B05D3/00
CPC分类号： B81C1/00698 , B81B2201/0292
摘要： A contiguous deep trench includes a first trench portion having a constant width between a pair of first parallel sidewalls, second and third trench portions each having a greater width than the first trench portion and laterally connected to the first trench portion. A non-conformal deposition process is employed to form a conductive layer that has a tapered geometry within the contiguous deep trench portion such that the conductive layer is not present on bottom surfaces of the contiguous deep trench. A gap fill layer is formed to plug the space in the first trench portion. The conductive layer is patterned into two conductive plates each having a tapered vertical portion within the first trench portion. After removing remaining portions of the gap fill layer, a device is formed that has a small separation distance between the tapered vertical portions of the conductive plates.
摘要翻译：连续的深沟槽包括在一对第一平行侧壁之间具有恒定宽度的第一沟槽部分，第二沟槽部分和第三沟槽部分各自具有比第一沟槽部分更大的宽度并横向连接到第一沟槽部分。使用非共形沉积工艺来形成导电层，该导电层在邻接的深沟槽部分内具有锥形几何形状，使得导电层不存在于邻接的深沟槽的底表面上。形成间隙填充层以堵塞第一沟槽部分中的空间。将导电层图案化为在第一沟槽部分内具有锥形垂直部分的两个导电板。在去除间隙填充层的剩余部分之后，形成在导电板的锥形垂直部分之间具有小间隔距离的装置。

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