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1. 发明申请

US20120040277A1 DAMASCENE RETICLE AND METHOD OF MANUFACTURE THEREOF 失效
标题翻译：大理石制品及其制造方法
公开(公告)号：US20120040277A1
公开(公告)日：2012-02-16
申请号：US13278571
申请日：2011-10-21
申请人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
发明人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
IPC分类号： G03F1/00 , B24B41/06
CPC分类号： G03F1/00 , G03F1/26 , G03F1/50
摘要： A reticle carrier for a polishing tool capable of accommodating a reticle includes a base plate with an obverse and reverse surfaces, a retaining ring secured to the obverse surface of the base plate forming a recess defined by the obverse surface of the rigid base plate and internal edges of the retaining ring. A reticle pad supports a reticle in the recess. The base plate and the reticle pad having an array of matching, aligned passageway holes therethrough for exhaustion of air from space between the base plate and a the reticle and for supply of air to that space so a vacuum can retain a the reticle in place on the reticle carrier under vacuum conditions and application of air under pressure can eject a reticle from the reticle carrier.
摘要翻译：用于能够容纳标线的抛光工具的掩模版载体包括具有正面和反面的基板，固定在基板的正面的保持环，形成由刚性基板的正面限定的凹部和内部固定环的边缘。掩模垫在凹槽中支撑掩模版。基板和标线垫具有一组匹配的对准的通孔，用于从底板和标线板之间的空间排出空气，并将空气供给到该空间，因此真空可以将该掩模版保持在适当的位置上在真空条件下的掩模版载体和在压力下施加空气可以从掩模版载体喷出掩模版。

2. 发明申请

US20080286660A1 DAMASCENE RETICLE AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：大理石制品及其制造方法
公开(公告)号：US20080286660A1
公开(公告)日：2008-11-20
申请号：US11749384
申请日：2007-05-16
申请人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
发明人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
IPC分类号： G03F1/00 , C09K3/14
CPC分类号： G03F1/00 , G03F1/26 , G03F1/50
摘要： A method for manufacturing an optical projection reticle employs a damascene process. First feature recesses are etched into a projection reticle mask plate which is transmissive or transparent. Then feature recesses are tilled with a radiation transmissivity modifying material comprising a partially transmissive material and/or a radiation absorber for absorbing actinic radiation. Sacrificial materials may be added to the recess temporarily prior to filling the recess to provide gaps juxtaposed with the material filling the recess. Thereafter, the sacrificial materials are removed. Then the projection mask is planarized leaving feature recesses filled with transmissivity modifying material, and any gaps desired. The projection mask is planarized while retained in a fixture holding it in place during polishing with a polishing tool and a slurry.
摘要翻译：光学投影掩模版的制造方法采用镶嵌工艺。第一特征凹槽被蚀刻到透射或透明的突出掩模掩模板中。然后，特征凹部用包括用于吸收光化辐射的部分透射材料和/或辐射吸收体的辐射透射率改性材料研磨。牺牲材料可以在填充凹部之前临时添加到凹部中，以提供与填充凹部的材料并置的间隙。此后，去除牺牲材料。然后将投影掩模平坦化，留下填充有透射率改性材料的特征凹部，以及任何期望的间隙。投影面罩被平坦化，同时保持在用抛光工具和浆料抛光过程中将其固定在位置的夹具中。

3. 发明授权

US08439728B2 Reticle carrier 失效
标题翻译：标线载体
公开(公告)号：US08439728B2
公开(公告)日：2013-05-14
申请号：US13278571
申请日：2011-10-21
申请人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
发明人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
IPC分类号： B24B41/06
CPC分类号： G03F1/00 , G03F1/26 , G03F1/50
摘要： A reticle carrier for a polishing tool capable of accommodating a reticle includes a base plate with an obverse and reverse surfaces, a retaining ring secured to the obverse surface of the base plate forming a recess defined by the obverse surface of the rigid base plate and internal edges of the retaining ring. A reticle pad supports a reticle in the recess. The base plate and the reticle pad having an array of matching, aligned passageway holes therethrough for exhaustion of air from space between the base plate and a the reticle and for supply of air to that space so a vacuum can retain a the reticle in place on the reticle carrier under vacuum conditions and application of air under pressure can eject a reticle from the reticle carrier.
摘要翻译：用于能够容纳标线的抛光工具的掩模版载体包括具有正面和反面的基板，固定在基板的正面的保持环，形成由刚性基板的正面限定的凹部和内部固定环的边缘。掩模垫在凹槽中支撑掩模版。基板和标线垫具有一组匹配的对准的通孔，用于从底板和标线板之间的空间排出空气，并将空气供给到该空间，因此真空可以将该掩模版保持在适当的位置上在真空条件下的掩模版载体和在压力下施加空气可以从掩模版载体喷出掩模版。

4. 发明授权

US08110321B2 Method of manufacture of damascene reticle 有权
标题翻译：镶嵌光罩的制造方法
公开(公告)号：US08110321B2
公开(公告)日：2012-02-07
申请号：US11749384
申请日：2007-05-16
申请人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
发明人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
IPC分类号： G03F1/16 , B24B5/00
CPC分类号： G03F1/00 , G03F1/26 , G03F1/50
摘要： A method for manufacturing an optical projection reticle employs a damascene process. First feature recesses are etched into a projection reticle mask plate which is transmissive or transparent. Then feature recesses are tilled with a radiation transmissivity modifying material comprising a partially transmissive material and/or a radiation absorber for absorbing actinic radiation. Sacrificial materials may be added to the recess temporarily prior to filling the recess to provide gaps juxtaposed with the material filling the recess. Thereafter, the sacrificial materials are removed. Then the projection mask is planarized leaving feature recesses filled with transmissivity modifying material, and any gaps desired. The projection mask is planarized while retained in a fixture holding it in place during polishing with a polishing tool and a slurry.
摘要翻译：光学投影掩模版的制造方法采用镶嵌工艺。第一特征凹槽被蚀刻到透射或透明的突出掩模掩模板中。然后，特征凹部用包括用于吸收光化辐射的部分透射材料和/或辐射吸收体的辐射透射率改性材料研磨。牺牲材料可以在填充凹部之前临时添加到凹部中，以提供与填充凹部的材料并置的间隙。此后，去除牺牲材料。然后将投影掩模平坦化，留下填充有透射率改性材料的特征凹部，以及任何期望的间隙。投影面罩被平坦化，同时保持在用抛光工具和浆料抛光过程中将其固定在位置的夹具中。

5. 发明授权

US06448629B2 Semiconductor device and method of making same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US06448629B2
公开(公告)日：2002-09-10
申请号：US09354742
申请日：1999-07-29
申请人： Rebecca D. Mih , Kevin S. Petrarca
发明人： Rebecca D. Mih , Kevin S. Petrarca
IPC分类号： H01L2906
CPC分类号： H01L21/0332 , H01L21/76224 , H01L21/7684
摘要： A second or cap dielectric layer is interposed between the usual or base dielectric layer and the metallic circuitry layer of a semiconductor device. The base dielectric layer has a plurality of recesses in an inactive part of the semiconductor device into which parts of the cap dielectric layer extend to interlock the cap dielectric layer to the base dielectric layer and to oppose shearing or tearing of the either (1) the metallic circuitry layer as the metallic circuitry layer is subjected to chemical-mechanical polishing, or (2) a hard mask layer from the base dielectric layer as the metallic circuitry layer is subjected to chemical-mechanical polishing.
摘要翻译：第二或盖电介质层介于通常的或基底电介质层与半导体器件的金属电路层之间。基极电介质层在半导体器件的非活性部分中具有多个凹部，盖电介质层的部分延伸以将盖电介质层与基底电介质层互锁，并且相对于（1）的剪切或撕裂金属电路层作为金属电路层进行化学机械抛光，或（2）当金属电路层进行化学机械抛光时，从基极介电层获得硬掩模层。

6. 发明授权

US06268261B1 Microprocessor having air as a dielectric and encapsulated lines and process for manufacture 失效
标题翻译：具有空气作为电介质的微处理器和封装线及其制造方法
公开(公告)号：US06268261B1
公开(公告)日：2001-07-31
申请号：US09185185
申请日：1998-11-03
申请人： Kevin S. Petrarca , Rebecca D. Mih
发明人： Kevin S. Petrarca , Rebecca D. Mih
IPC分类号： H01L2176
CPC分类号： H01L21/7682 , H01L21/764
摘要： A process for manufacturing a semiconductor circuit. The process comprises creating a plurality of adjacent conductive lines having a solid fill between the conductive lines; creating one or more layers above the lines and the fill; creating one or more pathways to the fill through the layers; and converting the fill to a gas that escapes through the pathways, leaving an air void between adjacent lines. To protect the lines from oxidation during processing, a related process for encapsulating conductive lines in one or more adhesion-promotion barrier layers may be performed. The encapsulation process may also be practiced in conjunction with other semiconductor manufacturing processes. The processes result in a multi-layer semiconductor circuit comprising conductive lines, wherein the lines have air as a dielectric between them, are encapsulated by an adhesion-promotion barrier layer, or both.
摘要翻译：一种制造半导体电路的工艺。该方法包括产生多条相邻的导线，其中导电线之间具有固体填充物; 在线和填充之上创建一个或多个层; 创建通过层的填充的一个或多个途径; 并将填充物转化为通过通道逸出的气体，在相邻管线之间留下空气。为了在加工过程中保护管线免受氧化，可以执行用于将导电线封装在一个或多个粘附促进阻挡层中的相关方法。封装过程也可以与其它半导体制造工艺一起实施。这些处理产生包括导线的多层半导体电路，其中线路之间具有作为电介质的空气，被粘附促进障碍层或二者包围。

7. 发明授权

US06429522B2 Microprocessor having air as a dielectric and encapsulated lines 有权
标题翻译：具有空气作为电介质和封装线的微处理器
公开(公告)号：US06429522B2
公开(公告)日：2002-08-06
申请号：US09742976
申请日：2000-12-20
申请人： Kevin S. Petrarca , Rebecca D. Mih
发明人： Kevin S. Petrarca , Rebecca D. Mih
IPC分类号： H01L2348
CPC分类号： H01L21/7682 , H01L21/764
摘要： A multi-layer semiconductor circuit comprising a plurality of conductive lines having air as a dielectric between the sides of the conductive lines in a first layer and having a structurally supportive non-metal cap layer at least partially covering the top of the conductive lines in the first layer and separating the air dielectric and conductive lines in the first layer from any subsequent layers. In a multi-layer semiconductor circuit with a plurality of conductive lines, at least the top, the bottom, and the opposite sides of each line are encapsulated by an adhesion-promotion barrier layer, and the barrier layer on the top of each conductive line has an upper surface that is flush with (a) a planar lower surface of a cap layer over the barrier layer, (b) a planar upper surface of a dielectric layer between the conductive lines, or (c) a combination thereof. The dielectric layer between the conductive lines may be air.
摘要翻译：一种多层半导体电路，包括多个导电线，其在第一层中在导电线的侧面之间具有空气作为电介质，并且具有至少部分地覆盖导电线的顶部的结构上支撑的非金属覆盖层第一层并且将第一层中的空气电介质和导电线与任何后续层分离。在具有多个导电线的多层半导体电路中，每条线的至少顶部，底部和相对侧被粘附促进障碍层包围，并且每条导线顶部的阻挡层具有与阻挡层上的（a）覆盖层的平坦下表面齐平的上表面，（b）导电线之间的介电层的平面上表面，或（c）其组合。导线之间的电介质层可以是空气。

8. 发明授权

US06258732B1 Method of forming a patterned organic dielectric layer on a substrate 失效
标题翻译：在基板上形成图案化的有机介电层的方法
公开(公告)号：US06258732B1
公开(公告)日：2001-07-10
申请号：US09244936
申请日：1999-02-04
申请人： Qinghuang Lin , Rebecca D. Mih , Kevin S. Petrarca
发明人： Qinghuang Lin , Rebecca D. Mih , Kevin S. Petrarca
IPC分类号： H01L21469
CPC分类号： H01L21/0335 , H01L21/31138 , H01L21/31144
摘要： An organic dielectric material is patterned on a substrate in a process utilizing a patterned resist which contains a metalloid or metallic element at the time of pattern transfer to the organic dielectric layer. The organic dielectric layer is preferably patterned using an oxygen etching process, most preferably oxygen reactive ion etching. The process advantageously avoids the need for a hard mask.
摘要翻译：有机电介质材料在图案转移到有机电介质层时利用包含准金属或金属元素的图案化抗蚀剂的工艺在衬底上图案化。有机介电层优选使用氧蚀刻工艺，最优选氧反应离子蚀刻来图案化。该方法有利地避免了对硬掩模的需要。

9. 发明授权

US06762667B2 Micro electromechanical switch having self-aligned spacers 失效
标题翻译：具有自对准间隔物的微机电开关
公开(公告)号：US06762667B2
公开(公告)日：2004-07-13
申请号：US10465451
申请日：2003-06-19
申请人： Richard P. Volant , David Angell , Donald F. Canaperi , Joseph T. Kocis , Kevin S. Petrarca , Kenneth J. Stein , William C. Wille
发明人： Richard P. Volant , David Angell , Donald F. Canaperi , Joseph T. Kocis , Kevin S. Petrarca , Kenneth J. Stein , William C. Wille
IPC分类号： H01H3752
CPC分类号： B81B3/001 , B81B2201/014 , H01H59/0009 , H01H2059/0072
摘要： A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction. The spacers are fabricated using standard semiconductor techniques typically used for the manufacture of CMOS devices. The present method of fabricating these spacers requires no added depositions, no extra lithography steps, and no additional etching.
摘要翻译：描述了一种制造和具有自对准间隔物或凸块的微机电开关（MEMS）装置的结构的方法。间隔件被设计成具有最佳尺寸并且被定位成使得它们用作开关的制动机构以最小化由静摩擦引起的问题。使用通常用于制造CMOS器件的标准半导体技术制造间隔物。制造这些间隔物的本方法不需要附加的沉积，不需要额外的光刻步骤，也不需要额外的蚀刻。

10. 发明授权

US06621392B1 Micro electromechanical switch having self-aligned spacers 有权
公开(公告)号：US06621392B1
公开(公告)日：2003-09-16
申请号：US10132743
申请日：2002-04-25
申请人： Richard P. Volant , David Angell , Donald F. Canaperi , Joseph T. Kocis , Kevin S. Petrarca , Kenneth J. Stein , William C. Wille
发明人： Richard P. Volant , David Angell , Donald F. Canaperi , Joseph T. Kocis , Kevin S. Petrarca , Kenneth J. Stein , William C. Wille
IPC分类号： H01H5122
CPC分类号： B81B3/001 , B81B2201/014 , H01H59/0009 , H01H2059/0072
摘要： A method of fabricating and the structure of a micro-electromechanical switch (MEMS) device provided with self-aligned spacers or bumps is described. The spacers are designed to have an optimum size and to be positioned such that they act as a detent mechanism for the switch to minimize problems caused by stiction. The spacers are fabricated using standard semiconductor techniques typically used for the manufacture of CMOS devices. The present method of fabricating these spacers requires no added depositions, no extra lithography steps, and no additional etching.

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