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91. 发明授权

US06469703B1 System of accessing data in a graphics system and method thereof 有权
标题翻译：在图形系统中访问数据的系统及其方法
公开(公告)号：US06469703B1
公开(公告)日：2002-10-22
申请号：US09347202
申请日：1999-07-02
申请人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
发明人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Antonio Asaro
IPC分类号： G06F15167
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the 10 controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.
摘要翻译：中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。此外，10个控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。由系统/图形控制器访问的统一的系统/图形存储器。统一存储器包含系统数据和图形数据。在具体实施例中，两个通道CH0和CH1访问统一存储器。每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。因此，每个通道可以同时访问图形数据，同时访问系统数据，或同时访问图形和系统数据。通过确保将物理地址划分为统一存储器内的块来实现同时访问，这样的数据块是相邻的块被不同的信道访问。

92. 发明授权

US06184908B2 Method and apparatus for co-processing video graphics data 失效
标题翻译：用于协处理视频图形数据的方法和装置
公开(公告)号：US06184908B2
公开(公告)日：2001-02-06
申请号：US09067512
申请日：1998-04-27
申请人： Jason CK Chan , Milivoje Aleksic , Antonio Asaro , James Doyle , Indra Laksono
发明人： Jason CK Chan , Milivoje Aleksic , Antonio Asaro , James Doyle , Indra Laksono
IPC分类号： G06F1500
CPC分类号： G06T15/005
摘要： To minimize CPU processing requirements for preparing and transferring data to a graphics processor, a graphics command processor is provided that supports application-level commands and references to the data associated with these commands. The graphics command processor parses the application command and data reference parameters, and subsequently fetches the appropriate graphics data from memory directly, without requiring additional CPU resources. To optimize performance, the graphics command processor fetches the data in parallel with the parsing and processing of the application commands from the CPU. The graphics command processor also includes a processing unit that converts the data from the format used by the application program to the format used for rendering. The graphics command processor creates the commands and data sequences used by a graphics engine to render each object of the image. Because the graphics command processor is closely coupled with the graphics engine, a number of efficiency can be gained, particularly with regard to the transfer of related data items. The processing of the primitive graphic command and data sequences by the graphics engine is asynchronous with the receipt of subsequent commands from the CPU and the fetching of subsequent data associated with the commands from the memory. In this manner, the latency associated with the conventional sequential processing of graphics data is minimized.
摘要翻译：为了最大限度地减少CPU处理对图形处理器的准备和传输数据的需求，提供了一个图形命令处理器，支持应用级命令和对与这些命令相关联的数据的引用。图形命令处理器解析应用程序命令和数据参考参数，然后直接从存储器中获取适当的图形数据，而不需要额外的CPU资源。为了优化性能，图形命令处理器从CPU解析和处理应用程序命令并行获取数据。图形命令处理器还包括处理单元，其将来自应用程序使用的格式的数据转换为用于呈现的格式。图形命令处理器创建由图形引擎使用以渲染图像的每个对象的命令和数据序列。因为图形命令处理器与图形引擎紧密耦合，所以可以获得许多效率，特别是关于相关数据项的传送。图形引擎对原始图形命令和数据序列的处理与从CPU接收后续命令以及从与存储器的命令相关联的后续数据的获取是异步的。以这种方式，与图形数据的常规顺序处理相关联的延迟最小化。

93. 发明授权

US06173367B2 Method and apparatus for accessing graphics cache memory 有权
标题翻译：访问图形缓存的方法和装置
公开(公告)号：US06173367B2
公开(公告)日：2001-01-09
申请号：US09314210
申请日：1999-05-19
申请人： Milivoje Aleksic , James Yee , Danny H. M Cheng , John DeRoo , Andrew E. Gruber
发明人： Milivoje Aleksic , James Yee , Danny H. M Cheng , John DeRoo , Andrew E. Gruber
IPC分类号： G06F1200
CPC分类号： G06F12/0857 , G06F12/0848 , G06F12/0875
摘要： A method and apparatus for utilizing a data cache in a system with both 2D and 3D graphics applications. In a specific embodiment of the present invention, a mode signal is received by the video system indicating whether a 2D or 3D application is to be used. Depending on the mode signal, either as a unified cache capable of being accessed by two separate data access streams, or two independent caches, each accessed by one data access stream.
摘要翻译：一种在具有2D和3D图形应用的系统中利用数据高速缓存的方法和装置。在本发明的具体实施例中，视频系统接收模式信号，指示是否使用2D或3D应用。根据模式信号，无论是作为能够被两个单独的数据访问流访问的统一高速缓存，还是两个独立的高速缓存，每个高速缓存由一个数据访问流访问。

94. 发明授权

US09285883B2 System and method to display content based on viewing orientation 有权
标题翻译：基于观看方向显示内容的系统和方法
公开(公告)号：US09285883B2
公开(公告)日：2016-03-15
申请号：US13038166
申请日：2011-03-01
申请人： Ning Bi , Milivoje Aleksic
发明人： Ning Bi , Milivoje Aleksic
IPC分类号： G09G5/00 , G06F3/01 , G06F1/16 , G06F3/0481 , G06F3/0483 , G06F3/0485
CPC分类号： G06F3/017 , G06F1/1694 , G06F3/011 , G06F3/012 , G06F3/04815 , G06F3/0483 , G06F3/0485
摘要： An apparatus and method for displaying content is disclosed. A particular method includes determining a viewing orientation of a user relative to a display and providing a portion of content to the display based on the viewing orientation. The portion includes at least a first viewable element of the content and does not include at least one second viewable element of the content. The method also includes determining an updated viewing orientation of the user and updating the portion of the content based on the updated viewing orientation. The updated portion includes at least the second viewable element. A display difference between the portion and the updated portion is non-linearly related to an orientation difference between the viewing orientation and the updated viewing orientation.
摘要翻译：公开了一种用于显示内容的装置和方法。一种特定的方法包括基于观看方向来确定用户相对于显示器的观看方向并且向显示器提供内容的一部分。该部分至少包括内容的第一可见元素，并且不包括内容的至少一个第二可见元素。该方法还包括确定用户的更新的观看方向并基于更新的观看方向来更新内容的部分。更新部分至少包括第二可见元素。该部分和更新部分之间的显示差异与观看方向和更新的观看方向之间的取向差异非线性相关。

95. 发明授权

US09230484B2 Adaptive backlight control and contrast enhancement 有权
标题翻译：自适应背光控制和对比度增强
公开(公告)号：US09230484B2
公开(公告)日：2016-01-05
申请号：US12203254
申请日：2008-09-03
申请人： Charles Leung , Jatin Naik , Lawrence Lim , Laurent Dahan , Milivoje Aleksic
发明人： Charles Leung , Jatin Naik , Lawrence Lim , Laurent Dahan , Milivoje Aleksic
IPC分类号： G09G3/36 , G09G3/34
CPC分类号： G09G3/3406 , G09G2320/064 , G09G2360/16
摘要： A transform function represented by at least n points that define n−1 regions is determined based at least in part on a first set of values associated with a display frame and a maximum average contrast function. The n points can be determined in response to a change in an average contrast of the display frame compared to an average contrast of a previous display frame exceeding a predetermined threshold. The first set of values is converted to a corresponding second set of values based on the transform function. A backlight control signal is generated based on an average contrast of the second set of values, whereby the backlight control signal is configured to control an intensity of a backlight of a display. Further, a video signal is generated based on the second set of values, whereby the video signal configured to drive the display.
摘要翻译：至少部分地基于与显示帧和最大平均对比度函数相关联的第一组值来确定定义n-1个区域的至少n个点的变换函数。可以响应于超过预定阈值的先前显示帧的平均对比度，显示帧的平均对比度的变化来确定n个点。基于变换函数将第一组值转换为相应的第二组值。基于第二组值的平均对比度产生背光控制信号，由此背光控制信号被配置为控制显示器的背光的强度。此外，基于第二组值生成视频信号，由此构成为驱动显示的视频信号。

96. 发明授权

US08924617B2 Memory device for providing data in a graphics system and method and apparatus therof 有权
标题翻译：用于在图形系统中提供数据的存储器件以及方法和装置
公开(公告)号：US08924617B2
公开(公告)日：2014-12-30
申请号：US12429833
申请日：2009-04-24
申请人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Anthony Asaro
发明人： Milivoje Aleksic , Raymond M. Li , Danny H. M. Cheng , Carl K. Mizuyabu , Anthony Asaro
IPC分类号： G06F13/14 , G09G5/39 , G06T1/60 , G09G5/393
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.
摘要翻译：中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。由系统/图形控制器访问的统一的系统/图形存储器。统一存储器包含系统数据和图形数据。在具体实施例中，两个通道CH0和CH1访问统一存储器。每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。

97. 发明申请

US20120137192A1 METHOD AND APPARATUS FOR ERROR MANAGEMENT 有权
公开(公告)号：US20120137192A1
公开(公告)日：2012-05-31
申请号：US13367059
申请日：2012-02-06
申请人： Sergiu Goma , Milivoje Aleksic
发明人： Sergiu Goma , Milivoje Aleksic
IPC分类号： H03M13/07 , G06F11/10 , H03M13/09
CPC分类号： H04L1/0057 , H03M13/19 , H03M13/27 , H04L1/0083
摘要： To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.

98. 发明申请

US20120019693A1 METHOD AND APPARATUS FOR PROCESSING BAD PIXELS 有权
标题翻译：用于处理边缘像素的方法和装置
公开(公告)号：US20120019693A1
公开(公告)日：2012-01-26
申请号：US13267677
申请日：2011-10-06
申请人： Sergiu Goma , Milivoje Aleksic
发明人： Sergiu Goma , Milivoje Aleksic
IPC分类号： H04N5/217
CPC分类号： H04N5/367
摘要： A technique for processing at least one bad pixel occurring in an image sensing system is provided. Dynamic bad pixel detection is performed on a plurality of streaming pixels taking from at least one controlled image and value and coordinate information for each bad pixel is subsequently stored as stored bad pixel information. Thereafter, static bad pixel correction may be performed based on the stored bad pixel information. The stored bad pixel information may be verified based on histogram analysis performed on the plurality of streaming pixels. The technique for processing bad pixels in accordance with the present invention may be embodied in suitable circuitry or, more broadly, within devices incorporating image sensing systems.
摘要翻译：提供了用于处理在图像感测系统中出现的至少一个不良像素的技术。对从至少一个受控图像获取的多个流像素执行动态坏像素检测，并且随后将每个坏像素的坐标信息存储为存储的不良像素信息。此后，可以基于存储的不良像素信息来执行静态坏像素校正。可以基于对多个流式像素执行的直方图分析来验证存储的不良像素信息。根据本发明的用于处理不良像素的技术可以体现在合适的电路中，或者更广泛地体现在包括图像感测系统的设备内。

99. 发明授权

US07770040B2 Method and apparatus for reducing power consumption of a co-processor by switching to low power dedicated memory in which image data is periodically updated 有权
标题翻译：通过切换到其中周期性更新图像数据的低功率专用存储器来减少协处理器的功耗的方法和装置
公开(公告)号：US07770040B2
公开(公告)日：2010-08-03
申请号：US11388928
申请日：2006-03-24
申请人： Milivoje Aleksic , Aris Balatsos , Charles Leung
发明人： Milivoje Aleksic , Aris Balatsos , Charles Leung
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , Y02D10/159
摘要： To provide reduced power consumption of a co-processor, a low power dedicated memory is provided. During a low power state, a processing component of the co-processor is instructed to use the low power dedicated memory and a first memory device, normally used by the processing component, is thereafter operated in a reduced power mode for the duration of the low power state. Preferably, the low power dedicated memory has a storage capacity that is significantly less than the storage capacity of the first memory. When an operating state other than the low power state is detected, normal power consumption by the first memory is resumed and the co-processor is directed to use the first memory once again. In this manner, the present invention allows co-processors, and preferably graphics co-processors, to operate in a beneficial low power mode thereby reducing power consumption.
摘要翻译：为了提供协处理器的降低的功耗，提供了低功率专用存储器。在低功率状态期间，指示协同处理器的处理部件使用低功率专用存储器，然后由处理部件通常使用的第一存储器件此后以低功率模式在低电平下持续工作电源状态优选地，低功率专用存储器具有明显小于第一存储器的存储容量的存储容量。当检测到除了低功率状态之外的操作状态时，第一存储器的正常功率消耗被恢复，并且协处理器被再次用于使用第一存储器。以这种方式，本发明允许协处理器，优选图形协处理器以有益的低功率模式操作，从而降低功耗。

100. 发明申请

US20090315899A1 GRAPHICS MULTI-MEDIA IC AND METHOD OF ITS OPERATION 有权
标题翻译：图形多媒体IC及其操作方法
公开(公告)号：US20090315899A1
公开(公告)日：2009-12-24
申请号：US12141358
申请日：2008-06-18
申请人： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
发明人： Fariborz Pourbigharaz , Sergiu Goma , Milivoje Aleksic , Andrzej Mamona
IPC分类号： G06T1/00 , G06F13/14
CPC分类号： G09G5/363 , G06F3/14 , G09G5/006 , G09G5/39 , G09G2330/021 , G09G2360/06 , G09G2370/04 , G09G2370/10 , H04N1/00278
摘要： A graphics multi-media integrated circuit (GMIC) is connected to a host processor over two serial links: a half duplex bi-directional serial link which accords to a protocol defined for a display serial interface, and a uni-directional serial link which accords to a compatible protocol defined for a camera serial interface. The GMIC receives packets according to the protocol from the host over the half duplex bi-directional serial link and processes these packets. The GMIC sends packets according to the protocol to the host over the uni-directional serial link. A packet from the host can request a processing operation by the GMIC or can initiate a memory operation at the memory of the GMIC. The GMIC can also send packets to the host to initiate a memory operation at the memory of the host. The GMIC may be connected to a display over a bi-directional serial link according to the display serial interface protocol and to a camera over a uni-directional serial link and a bi-directional control link according to the camera serial interface so that the host controls the display and camera indirectly through the GMIC.
摘要翻译：图形多媒体集成电路（GMIC）通过两个串行链路连接到主处理器：符合为显示串行接口定义的协议的半双工双向串行链路和符合协议的单向串行链路到为相机串行接口定义的兼容协议。 GMIC根据通过半双工双向串行链路的主机的协议接收数据包，并处理这些数据包。 GMIC根据协议将数据包通过单向串行链路发送到主机。来自主机的分组可以请求GMIC的处理操作，或者可以在GMIC的存储器处启动存储器操作。 GMIC还可以向主机发送数据包，以在主机的内存中启动内存操作。 GMIC可以根据显示串行接口协议通过双向串行链路连接到显示器，并且可以根据相机串行接口通过单向串行链路和双向控制链路连接到相机，使得主机通过GMIC间接控制显示和相机。

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