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91. 发明授权

US08785272B2 Process to make high-K transistor dielectrics 有权
标题翻译：制造高K晶体管电介质的工艺
公开(公告)号：US08785272B2
公开(公告)日：2014-07-22
申请号：US13224059
申请日：2011-09-01
申请人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Ming-Fang Wang , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L21/00 , H01L21/28 , H01L21/314
CPC分类号： H01L21/0228 , C23C16/56 , H01L21/02145 , H01L21/02153 , H01L21/02159 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/3141 , H01L21/31604 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/4966 , H01L29/517
摘要： A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.
摘要翻译：一种减少高k电介质层中的杂质的方法，包括以下步骤。提供基板。在衬底上形成具有杂质的高k电介质层。高k电介质层由MOCVD或ALCVD工艺形成。退火高k电介质层以减少高k电介质层内的杂质。

92. 发明授权

US08736142B2 Polarity switching circuit 有权
标题翻译：极性开关电路
公开(公告)号：US08736142B2
公开(公告)日：2014-05-27
申请号：US13568565
申请日：2012-08-07
申请人： Shih-Chang Chen
发明人： Shih-Chang Chen
IPC分类号： H02M7/5395
CPC分类号： B41J2/04581 , A61M2205/0294 , B41J2/04541 , H01L41/042 , H01L41/0973
摘要： A polarity switching circuit includes: a first current-limiting resistor and a second current-limiting resistor connected to a DC high voltage; a first transistor switch, a second transistor switch, a fourth transistor switch, and a fifth transistor switch respectively controlled by a first PWM signal and a second PWM signal; a third transistor and a sixth transistor switch whose control terminals are respectively connected to the first transistor switch and the fourth transistor switch; a first filter connected to the second transistor switch and the third transistor switch and a contact of a piezoelectric actuator; and a second filter connected to the fifth transistor switch and the sixth transistor switch and another contact of the piezoelectric actuator. When the first and the second PWM signal are switching between a high level and a low level, output AC voltages with smoothed AC waveforms are supplied to the contacts of the piezoelectric actuator.
摘要翻译：极性切换电路包括：连接到DC高电压的第一限流电阻和第二限流电阻; 分别由第一PWM信号和第二PWM信号控制的第一晶体管开关，第二晶体管开关，第四晶体管开关和第五晶体管开关; 第三晶体管和第六晶体管开关，其控制端子分别连接到第一晶体管开关和第四晶体管开关; 连接到第二晶体管开关和第三晶体管开关的第一滤波器和压电致动器的触点; 以及连接到第五晶体管开关和第六晶体管开关以及压电致动器的另一个触点的第二滤波器。当第一和第二PWM信号在高电平和低电平之间切换时，具有平滑的AC波形的输出AC电压被提供给压电致动器的触点。

93. 发明授权

US08397594B2 Feed drive mechanism and connecting assembly thereof 有权
标题翻译：进料驱动机构及其连接组件
公开(公告)号：US08397594B2
公开(公告)日：2013-03-19
申请号：US12629538
申请日：2009-12-02
申请人： Feng-Ming Ou , Jen-Ji Wang , Shih-Chang Chen , Chien-Chih Chiu , Yi-Huang Liou
发明人： Feng-Ming Ou , Jen-Ji Wang , Shih-Chang Chen , Chien-Chih Chiu , Yi-Huang Liou
IPC分类号： F16H25/22
CPC分类号： F16H25/24 , B23Q5/40 , F16H2025/2445 , Y10T74/18576 , Y10T74/18648 , Y10T403/3966
摘要： A feed drive mechanism and a connecting assembly thereof are described. The connecting assembly includes a main body and an outer sleeve. The main body has a connecting plate and an inner sleeve connected to a side surface of the connecting plate. Two opposite side surfaces of the connecting plate are respectively fixed on a screw nut seat and a lead screw nut of the feed drive mechanism, and a channel surrounds an outer side surface of the inner sleeve. The outer sleeve is sleeved on the outer side surface of the inner sleeve, enables the channel to be formed into a sealed space, and has an inlet and an outlet respectively communicating with the channel, thereby injecting a cooling medium into the channel.
摘要翻译：描述了馈送驱动机构及其连接组件。连接组件包括主体和外套筒。主体具有连接板和连接到连接板的侧表面的内套筒。连接板的两个相对的侧表面分别固定在进给驱动机构的螺母座和导螺杆螺母上，并且通道围绕内套筒的外侧表面。外套筒套在内套筒的外侧表面上，使得通道能够形成为密封空间，并且具有分别与通道连通的入口和出口，从而将冷却介质注入通道。

94. 发明授权

US08153526B2 High planarizing method for use in a gate last process 有权
标题翻译：用于门最后工艺的高平面化方法
公开(公告)号：US08153526B2
公开(公告)日：2012-04-10
申请号：US12499439
申请日：2009-07-08
申请人： Shen-Nan Lee , Huan-Just Lin , Shih-Chang Chen
发明人： Shen-Nan Lee , Huan-Just Lin , Shih-Chang Chen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： B24B37/042 , H01L21/28079 , H01L21/31053 , H01L21/3212 , H01L21/823807 , H01L21/823828 , H01L29/66545 , H01L29/7843
摘要： A method for performing a chemical-mechanical polishing (CMP) is provided. The method includes processing a semiconductor substrate to form a dummy gate structure on the substrate, to form a hard mask on the dummy gate structure, and to form a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer on the hard mask, performing a first CMP process with a first slurry to modify a non-planar topography of the ILD layer, performing a second CMP process with a second slurry to remove the hard mask, and performing a third CMP process with a third slurry to remove an interfacial layer that forms between the dummy gate and hard mask during semiconductor processing.
摘要翻译：提供了一种用于进行化学机械抛光（CMP）的方法。该方法包括处理半导体衬底以在衬底上形成虚拟栅极结构，以在虚拟栅极结构上形成硬掩模，并在硬的基底上形成接触蚀刻停止层（CESL）和层间电介质（ILD）层用第一浆料进行第一CMP处理以修饰ILD层的非平面形貌，用第二浆料进行第二CMP处理以除去硬掩模，以及用第三浆料进行第三CMP处理以除去在半导体处理期间在虚拟栅极和硬掩模之间形成的界面层。

95. 发明授权

US07482211B2 Junction leakage reduction in SiGe process by implantation 有权
标题翻译：通过植入SiGe工艺中的结漏电减少
公开(公告)号：US07482211B2
公开(公告)日：2009-01-27
申请号：US11523274
申请日：2006-09-19
申请人： Chun-Feng Nieh , Chien-Hao Chen , Keh-Chiang Ku , Tze-Liang Lee , Shih-Chang Chen
发明人： Chun-Feng Nieh , Chien-Hao Chen , Keh-Chiang Ku , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/00
CPC分类号： H01L29/7848 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7834
摘要： A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode on the gate dielectric, forming a stressor in the semiconductor substrate adjacent an edge of the gate electrode, and implanting an impurity after the step of forming the stressor. The impurity is preferably selected from the group consisting essentially of group IV elements, inert elements, and combinations thereof.
摘要翻译：提供一种形成半导体器件的方法。该方法包括提供半导体衬底，在半导体衬底上形成栅极电介质，在栅极电介质上形成栅电极，在与栅电极的边缘相邻的半导体衬底中形成应力器，并在形成步骤之后注入杂质压力源。杂质优选选自基本上由IV族元素，惰性元素及其组合组成的组。

96. 发明申请

US20080093682A1 Polysilicon levels for silicided structures including MOSFET gate electrodes and 3D devices 审中-公开
标题翻译：硅栅结构的多晶硅层，包括MOSFET栅电极和3D器件
公开(公告)号：US20080093682A1
公开(公告)日：2008-04-24
申请号：US11583491
申请日：2006-10-18
申请人： Liang-Gi Yao , Jin Ying , Hun-Jan Tao , Shih-Chang Chen , Mong-Song Liang
发明人： Liang-Gi Yao , Jin Ying , Hun-Jan Tao , Shih-Chang Chen , Mong-Song Liang
IPC分类号： H01L29/76
CPC分类号： H01L21/823443 , H01L21/28097 , H01L21/823835 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/7833
摘要： Semiconductor structures having a silicided gate electrode and methods of manufacture are provided. A device comprises a first silicided structure formed in a first active region and a second silicided structure formed in a second active region. The two silicided structures have different metal concentrations. A method of forming a silicided device comprises forming a polysilicon structure on the first and second device fabrication regions. Embodiments include replacing a first portion of the polysilicon structure on the first device fabrication region with a metal and replacing a second portion of the polysilicon structure on the second device fabrication region with the metal. Preferably, the second portion is different than the first portion. Embodiments further include reacting the polysilicon structures on the first and second device fabrication regions with the metal to form a silicide.
摘要翻译：提供了具有硅化物栅电极和制造方法的半导体结构。一种器件包括形成在第一有源区中的第一硅化结构和形成在第二有源区中的第二硅化结构。两个硅化物结构具有不同的金属浓度。形成硅化器件的方法包括在第一和第二器件制造区域上形成多晶硅结构。实施例包括用金属替代第一器件制造区上的多晶硅结构的第一部分，并用金属代替第二器件制造区上的多晶硅结构的第二部分。优选地，第二部分不同于第一部分。实施例还包括使第一和第二器件制造区上的多晶硅结构与金属反应以形成硅化物。

97. 发明授权

US07361572B2 STI liner modification method 有权
标题翻译： STI衬垫修改方法
公开(公告)号：US07361572B2
公开(公告)日：2008-04-22
申请号：US11059728
申请日：2005-02-17
申请人： Chien-Hao Chen , Vincent S. Chang , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Vincent S. Chang , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/76235
摘要： A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of the trench surfaces using a nitrogen-containing gas prior to formation of the liner oxide layer, post-formation nitridation of the liner oxide layer, or both pre-treatment of the trench surfaces and post-formation nitridation of the liner oxide layer. The liner modification method of the present invention optimizes the inverse narrow width effect (INWE) and gate oxide integrity (GOI) of STI structures and prevents diffusion of dopant into the liner oxide layer during subsequent processing.
摘要翻译：公开了一种用于STI沟槽中的衬垫氧化物层的新的改进的衬垫修改方法。根据该方法，在衬底中蚀刻STI沟槽，并且通过氧化技术在沟槽表面上形成衬垫氧化物层。该方法还包括在形成衬垫氧化物层之前使用含氮气体预处理沟槽表面，衬里氧化物层的形成后氮化或沟槽表面的预处理和后形成氮化的衬里氧化物层。本发明的衬垫修改方法优化STI结构的反窄窄度效应（INWE）和栅极氧化物完整性（GOI），并防止掺杂剂在随后的处理期间扩散到衬里氧化物层中。

98. 发明授权

US07303996B2 High-K gate dielectric stack plasma treatment to adjust threshold voltage characteristics 有权
标题翻译：高K栅极电介质叠层等离子体处理来调节阈值电压特性
公开(公告)号：US07303996B2
公开(公告)日：2007-12-04
申请号：US10677158
申请日：2003-10-01
申请人： Ming-Fang Wang , Tuo-Hung Hou , Kai-Lin Mai , Liang-Gi Yao , Shih-Chang Chen
发明人： Ming-Fang Wang , Tuo-Hung Hou , Kai-Lin Mai , Liang-Gi Yao , Shih-Chang Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/28185 , H01L21/28167 , H01L21/28194 , H01L21/28202 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A method for treating a gate structure comprising a high-K gate dielectric stack to improve electric performance characteristics including providing a gate dielectric layer stack including a binary oxide over a silicon substrate; forming a polysilicon layer over the gate dielectric layer stack; lithographically patterning and etching to form a gate structure; and, carrying out at least one plasma treatment of the gate structure comprising a plasma source gas selected from the group consisting of H2, N2, O2, and NH3.
摘要翻译：一种用于处理包括高K栅极电介质堆叠的栅极结构以改善电性能特性的方法，包括在硅衬底上提供包括二元氧化物的栅极介电层堆叠; 在所述栅极介电层堆叠上形成多晶硅层; 光刻图案化和蚀刻以形成栅极结构; 以及进行至少一种栅极结构的等离子体处理，所述栅极结构包括选自H 2，N 2，O 2， / SUB>和NH 3。

99. 发明授权

US07262096B2 NAND flash memory cell row and manufacturing method thereof 有权
标题翻译： NAND闪存单元行及其制造方法
公开(公告)号：US07262096B2
公开(公告)日：2007-08-28
申请号：US11163818
申请日：2005-10-31
申请人： Shih-Chang Chen , Cheng-Yuan Hsu , Chih-Wei Hung
发明人： Shih-Chang Chen , Cheng-Yuan Hsu , Chih-Wei Hung
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/7881 , H01L29/7887
摘要： A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, inter-gate dielectric layer, a tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric layer, an erase gate and a first cap layer. Each of the second stacked gate structure has a select gate dielectric layer, a select gate and a second cap layer. The control gate is between each of the first stacked gate structures, and between each of the second stacked gate structures and the adjacent first stacked gate structure. The floating gate is between the control gate and substrate. The inter-gate dielectric layer is disposed between the control and floating gates. The tunnel oxide is between the floating gate and substrate. The doping regions are disposed under the first stacked gate structure, and the source/drain regions are in the exposed substrate.
摘要翻译： NAND闪存单元行包括第一和第二堆叠栅极结构，控制和浮置栅极，栅极间电介质层，隧道氧化物层，掺杂区域和源极/漏极区域。第一层叠栅极结构具有擦除栅极电介质层，擦除栅极和第一覆盖层。第二层叠栅极结构中的每一个具有选择栅极介电层，选择栅极和第二覆盖层。控制栅极位于每个第一层叠栅极结构之间，并且在第二层叠栅极结构中的每一个与相邻的第一层叠栅极结构之间。浮栅位于控制栅和基板之间。栅极间电介质层设置在控制栅极和浮栅之间。隧道氧化物位于浮栅和衬底之间。掺杂区域设置在第一层叠栅极结构之下，源极/漏极区域处于暴露的衬底中。

100. 发明授权

US07259050B2 Semiconductor device and method of making the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07259050B2
公开(公告)日：2007-08-21
申请号：US10834474
申请日：2004-04-29
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze Liang Lee , Shih-Chang Chen , Ju-Wang Hsu
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze Liang Lee , Shih-Chang Chen , Ju-Wang Hsu
IPC分类号： H01L21/338
CPC分类号： H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å per minute using the same etchant.
摘要翻译：半导体器件包括衬底，设置在衬底上的栅极和形成在栅极两侧的衬底中的源极和漏极。该器件还包括具有形成在栅极的侧壁上的第一层和第二层的薄间隔物，其中使用相同的蚀刻剂，第一层和第二层具有至少每分钟至少10埃的湿蚀刻速率。

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