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91. 发明授权

US5391511A Semiconductor processing method of producing an isolated polysilicon lined cavity and a method of forming a capacitor 失效
标题翻译：用于制造隔离多晶硅衬里腔的半导体加工方法和形成电容器的方法
公开(公告)号：US5391511A
公开(公告)日：1995-02-21
申请号：US891
申请日：1993-01-05
申请人： Trung T. Doan , Charles H. Dennison
发明人： Trung T. Doan , Charles H. Dennison
IPC分类号： H01L21/02 , H01L21/321 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L21/265
CPC分类号： H01L27/10817 , H01L21/02074 , H01L21/321 , H01L21/3212 , H01L21/76885 , H01L21/76889 , H01L27/10852 , H01L28/91 , Y10S438/906
摘要： A semiconductor processing includes: a) providing an area atop a semiconductor wafer to which electrical connection to a polysilicon containing component is to be made; b) providing a layer of first material atop the semiconductor wafer, the first material layer having an upper surface; c) providing a contact opening in the layer of first material to the area, the contact opening having a selected open cross dimension; d) providing a layer of polysilicon to a selected thickness atop the layer of first material and within the contact opening to contact the area, the selected thickness being less than one-half the open dimension such that polysilicon less than completely fills the contact opening and thereby defines an outwardly open polysilicon lined cavity; e) with the wafer having the polysilicon lined cavity outwardly open, chemical mechanical polishing with a chemical mechanical polishing slurry the polysilicon atop the first material layer to the upper first material layer surface to define an isolated polysilicon lined cavity; and f) removing chemical mechanical polishing slurry residuals from the outwardly open polysilicon lined cavity.
摘要翻译：一种半导体处理方法包括：a）在半导体晶片的顶部提供一个与要制造含多晶硅的元件电连接的区域; b）在半导体晶片的顶部提供第一材料层，第一材料层具有上表面; c）在所述区域的第一材料层中提供接触开口，所述接触开口具有选定的开放交叉尺寸; d）在所述第一材料层顶部和所述接触开口顶部提供选定厚度的多晶硅层以接触所述区域，所述选定厚度小于所述开口尺寸的一半，使得多晶硅不足以完全填充所述接触开口和从而限定向外开放的多晶硅衬里腔; e）当所述晶片具有向外打开的多晶硅衬里的空腔时，化学机械抛光通过化学机械抛光将多晶硅顶部到第一材料层表面以限定隔离的多晶硅衬里腔; 以及f）从向外开放的多晶硅衬里腔体去除化学机械抛光浆料残留物。

92. 发明授权

US5334862A Thin film transistor (TFT) loads formed in recessed plugs 失效
标题翻译：薄膜晶体管（TFT）负载形成在凹入插头中
公开(公告)号：US5334862A
公开(公告)日：1994-08-02
申请号：US104523
申请日：1993-08-10
申请人： Monte Manning , Charles H. Dennison
发明人： Monte Manning , Charles H. Dennison
IPC分类号： H01L21/336 , H01L29/786 , H01L29/68 , H01L21/265
CPC分类号： H01L29/66765 , H01L29/78621 , Y10S257/903
摘要： The invention is directed to a thin film transistor (TFT) fabricated by using a recessed planarized poly plug as the bottom gate and a recessed planarized poly plug for the TFT drain connecting region. The TFT of the present invention can be used in any integrated circuit that uses such devices and in particular as a pullup device in a static random access memory (SRAM). The invention is directed to a process to fabricate a thin film transistor (TFT) having LDDs and/or high resistive regions (loads) that are self-aligned to a recessed plug that is used as the bottom gate for the TFT. The thin film transistor (TFT) of the present invention fabricated on a supporting substrate, with the TFT comprising: a recessed conductive plug serving as a control gate; a control gate insulating layer; a non-recessed conductive plug serving as a source/drain region interconnect; a film of semiconductive material connecting to and overlapping the plugs, the film having vertical regions extending above the recessed plug and horizontal regions extending over the recessed and non-recessed plugs; wherein, the vertical regions above the recessed plug are conductively doped to form TFT source/drain regions and the horizontal region spanning between the vertical regions above the recessed plug is conductively doped to form a TFT channel region, the horizontal region above the non-recessed plug is conductively doped to form a TFT source/drain interconnect.
摘要翻译：本发明涉及通过使用凹陷平面化多晶硅塞作为底栅制造的薄膜晶体管（TFT）和用于TFT漏极连接区域的凹陷平面化多晶硅插头。本发明的TFT可用于任何使用这种装置的集成电路中，特别是作为静态随机存取存储器（SRAM）中的上拉器件。本发明涉及一种制造具有LDD和/或高电阻区域（负载）的薄膜晶体管（TFT）的方法，所述LDD和/或高电阻区域（负载）与用作TFT的底栅的凹陷插塞自对准。本发明的薄膜晶体管（TFT）制造在支撑基板上，TFT包括：用作控制栅的凹形导电插塞; 控制栅绝缘层; 用作源极/漏极区互连的非凹入的导电插塞; 连接到和重叠插塞的半导体材料的薄膜，该薄膜具有在凹形插头上方延伸的垂直区域和在凹入和非凹进的插头上延伸的水平区域; 其中，凹形插塞上方的垂直区域被导电掺杂以形成TFT源极/漏极区域，并且横跨在凹入插塞之上的垂直区域之间的水平区域被导电掺杂以形成TFT沟道区域，水平区域在非凹入插头导电掺杂以形成TFT源极/漏极互连。

93. 发明授权

US5292677A Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts 失效
标题翻译：用于制造用于接触的单个蚀刻停止层的叠层电容器多兆位动态随机存取存储器的减少掩模CMOS工艺
公开(公告)号：US5292677A
公开(公告)日：1994-03-08
申请号：US947523
申请日：1992-09-18
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91 , Y10S438/97
摘要： An etch stop layer is deposited on a DRAM wafer after formation of the PMOS and NMOS transistors and A.A's. After deposition of oxide 1, a first mask and etch process is used to form the capacitor container and remove the oxide 1 and etch stop at the future poly 1 and cell poly contacts. After deposition of the capacitor, a second mask and etch removes the capacitor layers at the future poly 1 contact. After deposition of oxide 2 and a poly etch stop layer, a third mask and etch process forms the bit line contact region through the cell poly, and the poly 1 and cell poly contact region. The etch is made through the cell poly at the bit line contact and a thin oxide is deposited and etched to form cell poly spacers that don't close off the active area. An oxide etch goes to the etch stop layer at the bit contact region, to the poly 1 at the future poly 1 contact, and to the cell poly at the future cell poly contact. After etch of the etch stop at the future bit line contact, the contacts are formed.
摘要翻译：在形成PMOS和NMOS晶体管和A.A之后，在DRAM晶片上沉积刻蚀停止层。在沉积氧化物1之后，使用第一掩模和蚀刻工艺来形成电容器容器，并且在未来的聚合物1和电池聚合物接触处除去氧化物1和蚀刻停止物。在电容器沉积之后，第二掩模和蚀刻在未来的poly 1接触处去除电容器层。在沉积氧化物2和多晶硅蚀刻停止层之后，第三掩模和蚀刻工艺通过电池多晶硅和聚合物1和电池多晶硅接触区域形成位线接触区域。通过在位线接触处的电池多晶硅进行蚀刻，并且沉积和蚀刻薄氧化物以形成不关闭有源区的电池聚间隔物。氧化物蚀刻在位接触区域处的蚀刻停止层，到未来聚1接触处的聚合物1，并在将来的电池聚接触处进入电池聚合物。在未来位线接触处蚀刻停止后，形成触点。

94. 发明授权

US5272367A Fabrication of complementary n-channel and p-channel circuits (ICs) useful in the manufacture of dynamic random access memories (drams) 失效
标题翻译：制造用于制造动态随机存取存储器（drams）的互补n沟道和p沟道电路（IC）
公开(公告)号：US5272367A
公开(公告)日：1993-12-21
申请号：US988376
申请日：1992-12-07
申请人： Charles H. Dennison , Tyler A. Lowrey
发明人： Charles H. Dennison , Tyler A. Lowrey
IPC分类号： H01L21/334 , H01L21/762 , H01L21/8238 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10844 , H01L21/76218 , H01L21/823892 , H01L27/10805 , H01L27/10808 , H01L27/10852 , H01L27/10873 , H01L29/66181 , H01L27/105 , Y10S257/90
摘要： A process for fabricating n-channel and p-channel metal-oxide-semiconductor devices in the manufacture of very large scale integrated circuits, such as high density dynamic random access memories (DRAMs). n-channel and p-channel gate layers of selected conductive and non-conductive materials are initially formed on the surface of a semiconductor substrate, and the n-channel gate layers in a memory array and periphery section of the substrate are initially photodefined, leaving the p-channel gate layers in place over an area of the substrate where future p-channel transistors and P+ active area will be formed. A series of ion implantation steps are then carried out to form the n-channel transistors, therefor using no masking steps, since the in-place gate layers on the p-channel peripheral section serves as an ion implantation mask over this section and thus prevents n-type ions from entering the p-type transistor areas of the peripheral section. Then, the completed n-channel transistors memory section is appropriately masked prior to photo-defining the transistor gate electrodes for either p or n-type transistors in the peripheral section of the substrate. Using this process, not only are the total number of necessary ion implantation masking steps held to an absolute minimum, but the p-channel peripheral section circuits such as sense amplifiers, decoders and drivers, logic circuits, and the like are exposed to a minimum of temperature cycling, thereby enhancing device reliability and improving the high frequency performance of the devices thus produced.
摘要翻译：用于制造诸如高密度动态随机存取存储器（DRAM）的非常大规模集成电路的制造n沟道和p沟道金属氧化物半导体器件的工艺。选择的导电和非导电材料的n沟道和p沟道栅极层初始形成在半导体衬底的表面上，并且存储器阵列中的n沟道栅极层和衬底的外围部分最初被定义，留下 p沟道栅极层位于衬底的将要形成未来p沟道晶体管和P +有源区的区域上。然后执行一系列离子注入步骤以形成n沟道晶体管，因此不使用掩模步骤，因为p沟道外围部分上的就地栅极层用作该部分上的离子注入掩模，因此防止 n型离子进入周边部分的p型晶体管区域。然后，在对衬底的周边部分中的p型或n型晶体管的晶体管栅电极进行光电定义之前，完成的n沟道晶体管存储部分被适当地屏蔽。使用该过程，不仅将必要的离子注入掩模步骤的总数保持为绝对最小值，而且将诸如读出放大器，解码器和驱动器，逻辑电路等的p沟道外围部分电路暴露于最小的温度循环，从而提高器件的可靠性并提高由此产生的器件的高频性能。

95. 发明授权

US5155057A Stacked v-cell capacitor using a disposable composite dielectric on top of a digit line 失效
标题翻译：使用数字线顶部的一次性复合电介质堆叠的v电池电容器
公开(公告)号：US5155057A
公开(公告)日：1992-10-13
申请号：US609281
申请日：1990-11-05
申请人： Charles H. Dennison , Pierre C. Fazan , Ruojia Lee , Yauh-Ching Liu
发明人： Charles H. Dennison , Pierre C. Fazan , Ruojia Lee , Yauh-Ching Liu
IPC分类号： H01L27/108
CPC分类号： H01L27/10817
摘要： A stacked v-cell (SVC) capacitor using a modified stacked capacitor storage cell fabrication process. The SVC capacitor is made up of a polysilicon structure, having a v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 70% without enlarging the surface area defined for a normal stacked capacitor cell.
摘要翻译：使用改进的堆叠电容器存储单元制造工艺的堆叠的v电池（SVC）电容器。 SVC电容器由具有V形横截面的多晶硅结构构成，该多晶硅结构位于掩埋接触处，并且延伸到由多晶硅覆盖的相邻存储节点，介电夹在其间。多晶硅结构的添加增加了存储能力70％，而不会扩大为正常层叠电容器单元所定义的表面积。

96. 发明授权

US4981810A Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers 失效
标题翻译：用于产生具有减小斜率，阶梯轮廓侧壁间隔物的场效应晶体管的方法
公开(公告)号：US4981810A
公开(公告)日：1991-01-01
申请号：US481096
申请日：1990-02-16
申请人： Pierre C. Fazan , Charles H. Dennison , Ruojia Lee , Yauh-Ching Liu
发明人： Pierre C. Fazan , Charles H. Dennison , Ruojia Lee , Yauh-Ching Liu
IPC分类号： H01L21/336 , H01L21/768 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/78 , Y10S257/90
摘要： The present invention utilizes a wet or vapor isotropic etchback process of carefully controlled duration to create a field-effect transistor having reduced-slope, staircase-profile sidewall spacers formed from a pair of TEOS oxide layers. The spacer's reduced sidewall slope and staircase profile facilitates digit line deposition and aids in reducing the existence of short-prone polysilicon stringers.
摘要翻译：本发明利用仔细控制的持续时间的湿或蒸汽各向同性回蚀工艺，以产生具有由一对TEOS氧化物层形成的具有减小斜率，阶梯型侧壁间隔物的场效应晶体管。间隔件减少的侧壁倾斜和阶梯轮廓有助于数字线沉积，有助于减少短路多晶硅桁架的存在。

97. 发明授权

US08030734B2 Forming phase change memories with a breakdown layer sandwiched by phase change memory material 有权
标题翻译：形成具有夹层相变记忆材料的击穿层的相变存储器
公开(公告)号：US08030734B2
公开(公告)日：2011-10-04
申请号：US12346507
申请日：2008-12-30
申请人： Charles H. Dennison , George A. Gordon , John Peters
发明人： Charles H. Dennison , George A. Gordon , John Peters
IPC分类号： H01L21/82 , H01L21/20 , H01L29/00
CPC分类号： H01L45/06 , H01L27/2427 , H01L45/1233 , H01L45/1246 , H01L45/126 , H01L45/144 , H01L45/1683
摘要： A phase change memory cell may be formed with a pair of chalcogenide phase change layers that are separated by a breakdown layer. The breakdown layer may be broken down prior to use of the memory so that a conductive breakdown point is defined within the breakdown layer. In some cases, the breakdown point may be well isolated from the surrounding atmosphere, reducing heat losses and decreasing current consumption. In addition, in some cases, the breakdown point may be well isolated from overlying and underlying electrodes, reducing issues related to contamination. The breakdown point may be placed between a pair of chalcogenide layers with the electrodes outbound of the two chalcogenide layers.
摘要翻译：相变存储单元可以由被击穿层分开的一对硫族化物相变层形成。在使用存储器之前可以将击穿层分解，使得在击穿层内限定导电击穿点。在某些情况下，故障点可能与周围大气良好隔离，减少热损失和降低电流消耗。此外，在某些情况下，击穿点可能与上覆电极和下层电极很好地隔离，从而减少与污染有关的问题。击穿点可以放置在一对硫族化物层之间，其中两个硫族化物层的电极出发。

98. 发明授权

US07804082B2 Phase change memory system 有权
标题翻译：相变存储器系统
公开(公告)号：US07804082B2
公开(公告)日：2010-09-28
申请号：US11998899
申请日：2007-12-03
申请人： Charles H. Dennison
发明人： Charles H. Dennison
IPC分类号： H01L29/02
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L45/06 , H01L45/12 , H01L45/1233 , H01L45/144
摘要： A thin film phase change memory may be provided with a layer which changes between amorphous and crystalline states. The threshold voltage of that layer may be increased in a variety of fashions. As a result of the threshold increase, it is possible to transition cells, initially fabricated in the set or low resistance state, into the reset or high resistance state. In one advantageous embodiment, after such initialization and programming, the threshold voltage increase is eliminated so that the cells operate thereafter without the added threshold voltage.
摘要翻译：薄膜相变存储器可以设置有在非晶态和晶态之间变化的层。该层的阈值电压可以以各种方式增加。作为门限增加的结果，可以将初始以设定或低电阻状态制造的电池转换成复位或高电阻状态。在一个有利的实施例中，在这样的初始化和编程之后，消除阈值电压增加，使得在没有增加的阈值电压的情况下，电池工作。

99. 发明申请

US20100197120A1 Forming Phase Change Memory Cell With Microtrenches 审中-公开
标题翻译：形成相变存储器细胞与微螺旋
公开(公告)号：US20100197120A1
公开(公告)日：2010-08-05
申请号：US12756392
申请日：2010-04-08
申请人： Fabio Pellizzer , Charles H. Dennison
发明人： Fabio Pellizzer , Charles H. Dennison
IPC分类号： H01L21/20
CPC分类号： H01L45/06 , H01L27/2427 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1691
摘要： A semiconductor substrate is covered by a dielectric region. The dielectric region accommodates a memory element and a selection element forming a phase change memory cell. The memory element is formed by a resistive element and by a storage region of a phase change material extending on and in contact with the resistive element at a contact area. The selection element is formed by a switching region of chalcogenic material embedded in the dielectric region and belonging to a stack extending on the resistive element and including also the storage region. A mold region extends on top of the resistive element and delimits a trench having a substantially elongated shape. At least one portion of the storage region extends in the trench and defines a phase change memory portion over the contact area.
摘要翻译：半导体衬底被电介质区域覆盖。电介质区域容纳存储元件和形成相变存储单元的选择元件。存储元件由电阻元件和在接触区域处延伸并与电阻元件接触的相变材料的存储区域形成。选择元件由嵌入在电介质区域中的属于在电阻元件上延伸并且还包括存储区域的堆叠的金属的切换区域形成。模具区域在电阻元件的顶部延伸并限定具有基本细长形状的沟槽。存储区域的至少一部分在沟槽中延伸并限定了接触区域上的相变存储部分。

100. 发明授权

US07729162B2 Semiconductor phase change memory using multiple phase change layers 有权
标题翻译：半导体相变存储器使用多个相变层
公开(公告)号：US07729162B2
公开(公告)日：2010-06-01
申请号：US11973565
申请日：2007-10-09
申请人： Charles H. Dennison , Stephen J. Hudgens
发明人： Charles H. Dennison , Stephen J. Hudgens
IPC分类号： G11C11/00
CPC分类号： H01L45/065 , G11C13/0004 , H01L27/2427 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1625 , Y10S977/754
摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
摘要翻译：根据一些实施例，可以形成相变存储器，其中减少了编程体积相变材料之外的区域中的热导率。这可能会降低所得相变存储器的功耗。功耗的降低可以通过在编程体积之外形成很少或不混合的相变材料的不同层来实现。例如，在一个实施例中，可以在两个不同的相变层之间保持扩散阻挡层。在另一个实施方案中，可以使用面心立方硫属元素化合物结构。

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