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1. 发明授权

US5155057A Stacked v-cell capacitor using a disposable composite dielectric on top of a digit line 失效
标题翻译：使用数字线顶部的一次性复合电介质堆叠的v电池电容器
公开(公告)号：US5155057A
公开(公告)日：1992-10-13
申请号：US609281
申请日：1990-11-05
申请人： Charles H. Dennison , Pierre C. Fazan , Ruojia Lee , Yauh-Ching Liu
发明人： Charles H. Dennison , Pierre C. Fazan , Ruojia Lee , Yauh-Ching Liu
IPC分类号： H01L27/108
CPC分类号： H01L27/10817
摘要： A stacked v-cell (SVC) capacitor using a modified stacked capacitor storage cell fabrication process. The SVC capacitor is made up of a polysilicon structure, having a v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 70% without enlarging the surface area defined for a normal stacked capacitor cell.
摘要翻译：使用改进的堆叠电容器存储单元制造工艺的堆叠的v电池（SVC）电容器。 SVC电容器由具有V形横截面的多晶硅结构构成，该多晶硅结构位于掩埋接触处，并且延伸到由多晶硅覆盖的相邻存储节点，介电夹在其间。多晶硅结构的添加增加了存储能力70％，而不会扩大为正常层叠电容器单元所定义的表面积。

2. 发明授权

US4981810A Process for creating field effect transistors having reduced-slope, staircase-profile sidewall spacers 失效
标题翻译：用于产生具有减小斜率，阶梯轮廓侧壁间隔物的场效应晶体管的方法
公开(公告)号：US4981810A
公开(公告)日：1991-01-01
申请号：US481096
申请日：1990-02-16
申请人： Pierre C. Fazan , Charles H. Dennison , Ruojia Lee , Yauh-Ching Liu
发明人： Pierre C. Fazan , Charles H. Dennison , Ruojia Lee , Yauh-Ching Liu
IPC分类号： H01L21/336 , H01L21/768 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/78 , Y10S257/90
摘要： The present invention utilizes a wet or vapor isotropic etchback process of carefully controlled duration to create a field-effect transistor having reduced-slope, staircase-profile sidewall spacers formed from a pair of TEOS oxide layers. The spacer's reduced sidewall slope and staircase profile facilitates digit line deposition and aids in reducing the existence of short-prone polysilicon stringers.
摘要翻译：本发明利用仔细控制的持续时间的湿或蒸汽各向同性回蚀工艺，以产生具有由一对TEOS氧化物层形成的具有减小斜率，阶梯型侧壁间隔物的场效应晶体管。间隔件减少的侧壁倾斜和阶梯轮廓有助于数字线沉积，有助于减少短路多晶硅桁架的存在。

3. 发明授权

US5321648A Stacked V-cell capacitor using a disposable outer digit line spacer 失效
标题翻译：使用一次性外部数字线间隔器的堆叠V电池电容器
公开(公告)号：US5321648A
公开(公告)日：1994-06-14
申请号：US48168
申请日：1993-04-15
申请人： Charles H. Dennison , Pierre C. Fazan , Ruojia Lee , Yauh-Ching liu
发明人： Charles H. Dennison , Pierre C. Fazan , Ruojia Lee , Yauh-Ching liu
IPC分类号： H01L27/108 , G11C11/24
CPC分类号： H01L27/10817
摘要： A stacked v-cell (SVC) capacitor using a modified stacked capacitor storage cell fabrication process. The SVC capacitor is made up of polysilicon structure, having a v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 70% without enlarging the surface area defined for a normal stacked capacitor cell.
摘要翻译：使用改进的堆叠电容器存储单元制造工艺的堆叠的v电池（SVC）电容器。 SVC电容器由具有V形横截面的多晶硅结构组成，位于掩埋接触处并且延伸到由多晶硅覆盖的相邻存储节点之间，介电夹在其间。多晶硅结构的添加增加了存储能力70％，而不会扩大为正常层叠电容器单元所定义的表面积。

4. 发明授权

US5266513A Method of making stacked W-cell capacitor 失效
标题翻译：堆叠W电池电容的方法
公开(公告)号：US5266513A
公开(公告)日：1993-11-30
申请号：US978595
申请日：1992-11-19
申请人： Pierre C. Fazan , Charles H. Dennison , Ruojia Lee , Yauh-Ching Liu
发明人： Pierre C. Fazan , Charles H. Dennison , Ruojia Lee , Yauh-Ching Liu
IPC分类号： H01L27/108 , H01L21/70
CPC分类号： H01L27/10817
摘要： A stacked multi fingered cell (SMFC) capacitor using a modified stacked capacitor storage cell fabrication process. The SMFC is made up of polysilicon structure, having a multi-fingered cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.
摘要翻译：使用改进的堆叠电容器存储单元制造工艺的堆叠多指单元（SMFC）电容器。 SMFC由多晶硅结构组成，具有多指截面，位于掩埋接触处，并延伸到覆盖有多晶硅的相邻存储节点，介电夹在其间。多晶硅结构的添加增加了存储能力120％，而不会扩大为正常层叠电容器单元限定的表面积。

5. 发明授权

US5236855A Stacked V-cell capacitor using a disposable outer digit line spacer 失效
标题翻译：使用一次性外部数字线间隔器的堆叠V电池电容器
公开(公告)号：US5236855A
公开(公告)日：1993-08-17
申请号：US610493
申请日：1990-11-06
申请人： Charles H. Dennison , Pierre C. Fazan , Ruojia Lee , Yauh-Ching Liu
发明人： Charles H. Dennison , Pierre C. Fazan , Ruojia Lee , Yauh-Ching Liu
IPC分类号： H01L27/108
CPC分类号： H01L27/10817
摘要： A stacked v-cell (SVC) capacitor using a modified stacked capacitor storage cell fabrication process. The SVC capacitor is made up of polysilicon structure, having a v-shaped cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 70% without enlarging the surface area defined for a normal stacked capacitor cell.
摘要翻译：使用改进的堆叠电容器存储单元制造工艺的堆叠的v电池（SVC）电容器。 SVC电容器由具有V形横截面的多晶硅结构组成，位于掩埋接触处并且延伸到由多晶硅覆盖的相邻存储节点之间，介电夹在其间。多晶硅结构的添加增加了存储能力70％，而不会扩大为正常层叠电容器单元所定义的表面积。

6. 发明授权

US5196364A Method of making a stacked capacitor dram cell 失效
标题翻译：制造堆叠电容器DRAM单元的方法
公开(公告)号：US5196364A
公开(公告)日：1993-03-23
申请号：US602828
申请日：1990-10-24
申请人： Pierre C. Fazan , Charles H. Dennison , Ruojia Lee , Yauh-Ching Liu
发明人： Pierre C. Fazan , Charles H. Dennison , Ruojia Lee , Yauh-Ching Liu
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817
摘要： A stacked multi-fingered cell (SMFC) capacitor using a modified stacked capacitor storage cell fabrication process. The (SMFC) is made up of polysilicon structure, having a multi-fingered cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.
摘要翻译：使用改进的堆叠电容器存储单元制造工艺的堆叠多指单元（SMFC）电容器。（SMFC）由具有多指截面的多晶硅结构构成，位于掩埋接触处，并延伸到由多晶硅覆盖的相邻存储节点之间，电介质夹在其间。多晶硅结构的添加增加了存储能力120％，而不会扩大为正常层叠电容器单元限定的表面积。

7. 发明授权

US5013680A Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography 失效
标题翻译：用于制造具有超越可用光刻的分辨率极限的特征宽度的DRAM阵列的工艺
公开(公告)号：US5013680A
公开(公告)日：1991-05-07
申请号：US555980
申请日：1990-07-18
申请人： Tyler A. Lowrey , Randal W. Chance , D. Mark Durcan , Ruojia Lee , Charles H. Dennison , Yauh-Ching Liu , Pierre C. Fazan , Fernando Gonzalez , Gordon A. Haller
发明人： Tyler A. Lowrey , Randal W. Chance , D. Mark Durcan , Ruojia Lee , Charles H. Dennison , Yauh-Ching Liu , Pierre C. Fazan , Fernando Gonzalez , Gordon A. Haller
IPC分类号： H01L21/033 , H01L21/308 , H01L21/334 , H01L21/336 , H01L21/762 , H01L21/768 , H01L21/8242
CPC分类号： H01L27/10864 , H01L21/033 , H01L21/3086 , H01L21/76232 , H01L21/768 , H01L29/66181 , H01L29/66666 , Y10S438/947
摘要： A process for creating a DRAM array having feature widths that transcend the resolution limit of the employed photolithographic process using only five photomasking steps. The process involves the following steps: creation of a half-pitch hard-material mask that is used to etch a series of equidistanty-spaced isolation trenches in a silicon substrate; filling the isolation trenches with insulative material; creation of a hard-material mask consisting of strips that are 1-1/2F in width, separated by spaces that are 1/2F in width, that is used to etch a matrix of storage trenches; angled implantation of a N-type impurity in the storage trench walls; another anisotropic etch to deepen the storage trenches; deposition of a capacitor dielectric layer; deposition of a protective polysilicon layer on top of the dielectric layer; removal of the dielectric layer and the protective polysilicon layer at the bottom of each storage trench with a further anisotropic etch; filling the storage trenches with in-situ-doped polysilicon; planarization down to the substrate level; creation of an access gate on opposite sides of each storage trench, in addition to wordlines which interconnect gates within array columns by anisotropically etching a conformal conductive layer that has been deposited on top of oxide-silicon mesas that run perpendicular to the isolation trenches and are centered between the rows of storage trenches, the oxide-silicon mesas having been created with an etch using a photoresist mask consisting of a series of parallel strips that have been laid down with minimum feature and space width, then plasma etched to 3/4F; creation of source and drains with an N-type implant; and anisotropically etching the metal layer to create bitlines along the sidewalls of the oxide mesas.
摘要翻译：一种用于创建DRAM阵列的方法，其具有仅使用五个光掩模步骤超越所使用的光刻工艺的分辨率极限的特征宽度。该方法包括以下步骤：产生半间距硬材料掩模，其用于蚀刻硅衬底中的一系列等间隔隔开的隔离沟槽; 用绝缘材料填充隔离沟; 由宽度为1-1 / 2F的条形成的宽度为1 / 2F的间隔的用于蚀刻存储沟槽的矩阵的硬质材料掩模的形成; 在存储沟槽壁中倾斜注入N型杂质; 另一种各向异性蚀刻来加深存储沟槽; 沉积电容器电介质层; 保护性多晶硅层在电介质层的顶部上沉积; 通过进一步的各向异性蚀刻在每个存储沟槽的底部去除电介质层和保护性多晶硅层; 用原位掺杂多晶硅填充存储沟槽; 平坦化到底层水平; 在每个存储沟槽的相对侧上形成存取栅极，除了通过各向异性蚀刻已经沉积在垂直于隔离沟槽的氧化物 - 硅台面顶部上的共形导电层来互连阵列列内的栅极的字线之外，并且是在存储沟槽的行之间居中，使用由具有最小特征和空间宽度放置的一系列平行条组成的光刻胶掩模，然后将等离子体蚀刻到3 / 4F，利用蚀刻产生氧化物 - 硅台面; 用N型植入物创建源和排水沟; 并各向异性地蚀刻金属层以沿着氧化物台面的侧壁产生位线。

8. 发明授权

US5084406A Method for forming low resistance DRAM digit-line 失效
标题翻译：低电阻DRAM数位线形成方法
公开(公告)号：US5084406A
公开(公告)日：1992-01-28
申请号：US724026
申请日：1991-07-01
申请人： Howard E. Rhodes , Pierre C. Fazan , Hiang C. Chan , Charles H. Dennison , Yauh-Ching Liu
发明人： Howard E. Rhodes , Pierre C. Fazan , Hiang C. Chan , Charles H. Dennison , Yauh-Ching Liu
IPC分类号： G11C11/401 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/10 , H01L27/108
CPC分类号： H01L23/53271 , H01L21/768 , H01L23/5283 , H01L2924/0002
摘要： A DRAM fabrication process is disclosed for constructing a reduced resistance digit-line. The digit-line is so constructed as to maintain low resistance as it crosses the gaps between word-lines. By bridging gaps having a dimension less than or falling below a calculated critical gap spacing, and following the contours of gaps having a dimension greater or falling above that critical gap dimension, the digit-line resistance can be minimized.
摘要翻译：公开了用于构造减小电阻数字线的DRAM制造工艺。数字线被构造成当它跨越字线之间的间隙时保持低电阻。通过桥接具有小于或低于计算的临界间隙的尺寸的间隙，并且跟随具有大于或低于该临界间隙尺寸的尺寸的间隙的轮廓，可以使数字线电阻最小化。

9. 发明授权

US5234855A Stacked comb spacer capacitor 失效
标题翻译：堆叠梳间隔电容器
公开(公告)号：US5234855A
公开(公告)日：1993-08-10
申请号：US633595
申请日：1990-12-21
申请人： Howard E. Rhodes , Hiang C. Chan , Charles H. Dennison , Yauh-Ching Liu , Pierre C. Fazan , Gurtej S. Sandhu
发明人： Howard E. Rhodes , Hiang C. Chan , Charles H. Dennison , Yauh-Ching Liu , Pierre C. Fazan , Gurtej S. Sandhu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87 , H01L28/91
摘要： A stacked comb spacer capacitor (SCSC) using a modified stacked capacitor storage cell fabrication process. The SCSC is made up of polysilicon structure, having a spiked v-shaped (or comb-shaped) cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The creation of the spiked polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell. Removing the dielectric residing under the backside of the storage node cell plate and filling that area with polysilicon increases storage capacity by an additional 50% or more.
摘要翻译：使用改进的堆叠电容器存储单元制造工艺的堆叠梳状间隔电容器（SCSC）。 SCSC由多晶硅结构组成，具有加深的V形（或梳状）横截面，位于掩埋接触处，并延伸到由多晶硅覆盖的相邻存储节点和介于其间的电介质。掺杂多晶硅结构的产生增加了存储能力50％，而不会扩大为正常埋地数字线叠层电容器单元定义的表面积。去除位于存储节点单元板背面的电介质并用多晶硅填充该区域将存储容量提高了50％以上。

10. 发明授权

US5170233A Method for increasing capacitive surface area of a conductive material in semiconductor processing and stacked memory cell capacitor 失效
标题翻译：用于增加半导体处理中的导电材料的电容表面积的方法和堆叠的存储单元电容器
公开(公告)号：US5170233A
公开(公告)日：1992-12-08
申请号：US722854
申请日：1991-06-27
申请人： Yauh-Ching Liu , Pierre C. Fazan , Hiang C. Chan , Charles H. Dennison , Howard E. Rhodes
发明人： Yauh-Ching Liu , Pierre C. Fazan , Hiang C. Chan , Charles H. Dennison , Howard E. Rhodes
IPC分类号： H01L21/02 , H01L27/108 , H01L29/92
CPC分类号： H01L27/10817 , H01L28/87 , H01L28/90
摘要： A method of fabricating a semiconductor wafer comprises providing an electrically conductive area on a semiconductor wafer. Multiple alternating layers of first and second materials are provided atop the wafer. The first and second materials need be selectively etchable relative to one another. The multiple layers are etched and the electrically conductive area upwardly exposed to define exposed edges of the multiple layers projecting upwardly from the electrically conductive area. One of the first or second materials is selectively isotropically etched relative to the other to produce indentations which extend generally laterally into the exposed edges of the multiple layers. A layer of electrically conductive material is applied atop the wafer and electrically conductive area, and fills the exposed edge indentations. The electrically conductive material is etched to leave conductive material extending upwardly from the electrically conductive area adjacent the multiple layer edges and within the indentations. The multiple layers are etched from the wafer to leave upwardly projecting conductive material having lateral projections extending therefrom. Such material is used to form the lower plate of a capacitor.
摘要翻译：制造半导体晶片的方法包括在半导体晶片上提供导电区域。将第一和第二材料的多个交替层设置在晶片顶部。第一和第二材料需要相对于彼此可选择性地蚀刻。蚀刻多个层，并且导电区域向上暴露以限定从导电区域向上突出的多个层的暴露边缘。第一或第二材料之一相对于另一材料选择性地各向同性地蚀刻，以产生大致横向延伸到多层的暴露边缘的凹痕。将一层导电材料施加在晶片和导电区域顶部，并填充暴露的边缘凹陷。蚀刻导电材料以留下从邻近多层边缘和凹陷内的导电区域向上延伸的导电材料。从晶片上蚀刻多层以留下向上突出的具有从其延伸的侧向突起的导电材料。这种材料用于形成电容器的下板。

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