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91. 发明授权

US07759772B2 Method to form Si-containing SOI and underlying substrate with different orientations 失效
标题翻译：形成含Si的SOI和具有不同取向的下层衬底的方法
公开(公告)号：US07759772B2
公开(公告)日：2010-07-20
申请号：US11550681
申请日：2006-10-18
申请人： Meikei Ieong , Devendra K. Sadana , Ghavam Shahidi
发明人： Meikei Ieong , Devendra K. Sadana , Ghavam Shahidi
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L21/76251 , H01L21/2007
摘要： A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing layers or through an interface located between the two Si-containing layers.
摘要翻译：一种形成包含上层含Si层和下层含Si层的混合SOI衬底的方法，其中上层含Si层和下层含Si层具有不同的结晶取向。根据本发明，掩埋绝缘区域可以位于一个含硅层内或通过位于两个含Si层之间的界面。

92. 发明申请

US20100112800A1 CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS 有权
标题翻译： CMOS结构及其使用多种晶体取向和栅极材料制造的方法
公开(公告)号：US20100112800A1
公开(公告)日：2010-05-06
申请号：US12683535
申请日：2010-01-07
申请人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
发明人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/28
CPC分类号： H01L21/28079 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/6659
摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.
摘要翻译：制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。平坦化层位于第二栅极材料层上。平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。也可以在第一栅极叠层上形成蚀刻停止层。所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

93. 发明授权

US07619300B2 Super hybrid SOI CMOS devices 失效
标题翻译：超级混合SOI CMOS器件
公开(公告)号：US07619300B2
公开(公告)日：2009-11-17
申请号：US12434247
申请日：2009-05-01
申请人： Meikei Ieong , Qiqing C. Ouyang
发明人： Meikei Ieong , Qiqing C. Ouyang
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207 , H01L29/7843
摘要： The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer. The dielectric material within the trench isolation region has lower stress compared to that is used in conventional STI process and it is laterally abuts at least the second stressed semiconductor surface layer and extends to an upper surface of the trench isolation region.
摘要翻译：本发明提供由混合取向的应力通道构成的半导体结构。特别地，半导体结构包括第一有源区，其具有位于掩埋绝缘材料的表面上的第一晶体取向的第一应力半导体表面层和具有位于第二晶体取向的第二应力半导体表面层的第二有源区在电介质材料的表面上。沟槽隔离区域位于第一和第二有源区域之间，并且沟槽隔离区域部分地填充有沟槽电介质材料和位于所述第二应力半导体表面层下方的电介质材料。与常规STI工艺中使用的沟槽隔离区域中的电介质材料相比具有较低的应力，并且它至少侧向邻接第二应力半导体表面层并且延伸到沟槽隔离区域的上表面。

94. 发明授权

US07605447B2 Highly manufacturable SRAM cells in substrates with hybrid crystal orientation 有权
标题翻译：具有混合晶体取向的基板中的高度可制造的SRAM单元
公开(公告)号：US07605447B2
公开(公告)日：2009-10-20
申请号：US11162780
申请日：2005-09-22
申请人： Bruce B. Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
发明人： Bruce B. Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
IPC分类号： H01L29/06 , H01L29/04 , H01L27/11
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903 , Y10S438/973
摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.
摘要翻译：本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于传输栅晶体管。

95. 发明授权

US07494861B2 Method for metal gated ultra short MOSFET devices 失效
标题翻译：金属门极超短MOSFET器件的方法
公开(公告)号：US07494861B2
公开(公告)日：2009-02-24
申请号：US12013704
申请日：2008-01-14
申请人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
发明人： Jack Oon Chu , Bruce B. Doris , Meikei Ieong , Jing Wang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7838 , H01L21/28017 , H01L29/105
摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.
摘要翻译：适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。体层掺杂了与地平面相反的杂质。栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

96. 发明申请

US20060145264A1 Stressed field effect transistors on hybrid orientation substrate 有权
标题翻译：混合取向衬底上强调场效应晶体管
公开(公告)号：US20060145264A1
公开(公告)日：2006-07-06
申请号：US11029797
申请日：2005-01-05
申请人： Dureseti Chidambarrao , Judson Holt , Meikei Ieong , Oiging Ouyang , Siddhartha Panda
发明人： Dureseti Chidambarrao , Judson Holt , Meikei Ieong , Oiging Ouyang , Siddhartha Panda
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/045 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.
摘要翻译：提供了具有改进的载流子迁移率的半导体结构。半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。本发明还提供了制造该方法的方法。一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道。

97. 发明授权

US06960806B2 Double gated vertical transistor with different first and second gate materials 失效
标题翻译：双门控垂直晶体管，具有不同的第一和第二栅极材料
公开(公告)号：US06960806B2
公开(公告)日：2005-11-01
申请号：US09886823
申请日：2001-06-21
申请人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
发明人： Andres Bryant , Meikei Ieong , K. Paul Muller , Edward J. Nowak , David M. Fried , Jed Rankin
IPC分类号： H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/78 , H01L29/786 , H01L29/76
CPC分类号： H01L29/4908 , H01L21/823842 , H01L27/092 , H01L29/66795 , H01L29/785
摘要： Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.
摘要翻译：因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

98. 发明授权

US06905941B2 Structure and method to fabricate ultra-thin Si channel devices 失效
标题翻译：制造超薄Si通道器件的结构和方法
公开(公告)号：US06905941B2
公开(公告)日：2005-06-14
申请号：US10250069
申请日：2003-06-02
申请人： Bruce B. Doris , Thomas S. Kanarsky , Meikei Ieong , Wesley C. Natzle
发明人： Bruce B. Doris , Thomas S. Kanarsky , Meikei Ieong , Wesley C. Natzle
IPC分类号： H01L21/762 , H01L21/84 , H01L21/76
CPC分类号： H01L21/84 , H01L21/76283
摘要： A method for preventing polysilicon stringer formation under the active device area of an isolated ultra-thin Si channel device is provided. The method utilizes a chemical oxide removal (COR) processing step to prevent stinger formation, instead of a conventional wet etch process wherein a chemical etchant such as HF is employed. A silicon-on-insulator (SOI) structure is also provided. The structure includes at least a top Si-containing layer located on a buried insulating layer; and an oxide filled trench isolation region located in the top Si-containing layer and a portion of the buried insulating layer. No undercut regions are located beneath the top Si-containing layer.
摘要翻译：提供了一种用于防止在隔离的超薄Si沟道器件的有源器件区域下形成多晶硅的方法。该方法使用化学氧化物去除（COR）处理步骤来防止托管架形成，而不是采用诸如HF的化学蚀刻剂的常规湿法蚀刻工艺。还提供了绝缘体上硅（SOI）结构。该结构包括至少位于掩埋绝缘层上的顶部含Si层; 以及位于顶部含Si层和掩埋绝缘层的一部分中的氧化物填充沟槽隔离区。顶部含Si层下方没有底切区域。

99. 发明授权

US06762469B2 High performance CMOS device structure with mid-gap metal gate 失效
标题翻译：高性能CMOS器件结构，具有中间间隙金属栅极
公开(公告)号：US06762469B2
公开(公告)日：2004-07-13
申请号：US10127196
申请日：2002-04-19
申请人： Anda C. Mocuta , Meikei Ieong , Ricky S. Amos , Diane C. Boyd , Dan M. Mocuta , Huajie Chen
发明人： Anda C. Mocuta , Meikei Ieong , Ricky S. Amos , Diane C. Boyd , Dan M. Mocuta , Huajie Chen
IPC分类号： H01L2976
CPC分类号： H01L21/823807 , H01L21/823828
摘要： High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.
摘要翻译：公开了具有中间间隙功函数金属栅极的高性能（表面沟道）CMOS器件，其中外延层用于PFET区域的阈值电压Vt调整/减小，用于大的Vt降低（〜500mV），如需要具有中间间隙金属栅极的CMOS器件。本发明提供了使用原位B掺杂外延层或B和C共掺杂外延层的反掺杂，其中C共掺杂提供了额外的自由度以减少B的扩散（也在随后的激活热循环期间））以保持浅的B剖面，这对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是至关重要的，同时保持良好的短沟道效应。对于具有中间间隙金属栅极的器件，B扩散曲线令人满意地浅，尖锐且具有高B浓度，以在栅极氧化物下提供并保持薄的高掺杂B层。

100. 发明授权

US06677646B2 Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS 有权
标题翻译：用于高性能凹槽通道CMOS的一次性反向间隔器工艺的方法和结构
公开(公告)号：US06677646B2
公开(公告)日：2004-01-13
申请号：US10117959
申请日：2002-04-05
申请人： Meikei Ieong , Omer H. Dokumaci , Thomas S. Kanarsky , Victor Ku
发明人： Meikei Ieong , Omer H. Dokumaci , Thomas S. Kanarsky , Victor Ku
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L29/456 , H01L29/4908 , H01L29/66545 , H01L29/66772 , H01L29/78618 , H01L29/78621
摘要： A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.
摘要翻译：一种高性能凹陷沟道CMOS器件，包括具有凹陷沟道区域和相邻的延伸注入区域和可选的晕轮植入区域的SOI层; 并且提供存在于SOI层顶上的至少一个栅极区域及其制造方法。邻接的延伸部分和可选的晕轮植入区域具有突然的侧向轮廓并且位于所述栅极区域下方。

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