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91. 发明申请

US20120235239A1 HYBRID MOSFET STRUCTURE HAVING DRAIN SIDE SCHOTTKY JUNCTION 有权
标题翻译：具有排水侧肖特基结的混合MOSFET结构
公开(公告)号：US20120235239A1
公开(公告)日：2012-09-20
申请号：US13049491
申请日：2011-03-16
申请人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/336 , H01L29/78
CPC分类号： H01L21/84 , H01L21/26506 , H01L21/26586 , H01L21/823814 , H01L21/823878 , H01L29/7839
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.
摘要翻译：一种形成晶体管器件的方法包括在半导体衬底上形成图案化的栅极结构，在邻近栅极结构的源极侧的半导体衬底上形成凸起的源极区域，并在图案化的栅极上形成凸起的源极区域上的硅化物接触并且在与栅极结构的漏极侧相邻的半导体衬底上。因此，限定了具有漏极侧肖特基接触和升高的源极侧欧姆接触的混合场效应晶体管（FET）结构。

92. 发明授权

US08263446B2 Asymmetric FinFET devices 有权
标题翻译：非对称FinFET器件
公开(公告)号：US08263446B2
公开(公告)日：2012-09-11
申请号：US12881152
申请日：2010-09-13
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/00
CPC分类号： H01L29/66795 , H01L21/2633 , H01L21/26506 , H01L21/26586 , H01L29/517 , H01L29/785 , H01L29/7855 , H01L29/7856
摘要： Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold-modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.
摘要翻译：公开了非对称FET器件，以及在翅片结构上制造这种非对称器件的方法。该制造方法包括在散热片上布置高k电介质层，随后是阈值修饰层，以倾斜角执行离子轰击，该倾斜角度在翅片的侧面之一上除去阈值修饰层。完成的FET器件将是不对称的，因为阈值修饰层仅存在于翅片一侧的两个器件之一中。在替代实施例中，引入另外的不对称性，再次使用倾斜离子注入，导致用于翅片每侧上的两个FinFET器件的不同的栅极 - 导体材料。

93. 发明授权

US08242549B2 Dynamic random access memory cell including an asymmetric transistor and a columnar capacitor 有权
标题翻译：包括非对称晶体管和柱状电容器的动态随机存取存储器单元
公开(公告)号：US08242549B2
公开(公告)日：2012-08-14
申请号：US12700807
申请日：2010-02-05
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Chengwen Pei , Geng Wang
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Chengwen Pei , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L21/823431 , H01L27/10823 , H01L27/1085 , H01L27/10876 , H01L27/10879 , H01L28/60 , H01L29/66795 , H01L29/785
摘要： A semiconductor fin having a doping of the first conductivity type and a semiconductor column are formed on a substrate. The semiconductor column and an adjoined end portion of the semiconductor fin are doped with dopants of a second conductivity type, which is the opposite of the first conductivity type. The doped semiconductor column constitutes an inner electrode of a capacitor. A dielectric layer and a conductive material layer are formed on the semiconductor fin and the semiconductor column. The conductive material layer is patterned to form an outer electrode for the capacitor and a gate electrode. A single-sided halo implantation may be performed. Source and drain regions are formed in the semiconductor fin to form an access transistor. The source region is electrically connected to the inner electrode of the capacitor. The access transistor and the capacitor collectively constitute a DRAM cell.
摘要翻译：在衬底上形成具有第一导电类型掺杂的半导体鳍和半导体柱。所述半导体柱和所述半导体鳍片的邻接端部掺杂有与所述第一导电类型相反的第二导电类型的掺杂剂。掺杂半导体柱构成电容器的内部电极。在半导体鳍片和半导体柱上形成介电层和导电材料层。图案化导电材料层以形成用于电容器的外部电极和栅电极。可以进行单侧晕圈植入。源极和漏极区域形成在半导体鳍片中以形成存取晶体管。源极区域电连接到电容器的内部电极。存取晶体管和电容器共同构成DRAM单元。

94. 发明授权

US08198169B2 Deep trench capacitor in a SOI substrate having a laterally protruding buried strap 有权
标题翻译： SOI衬底中的深沟槽电容器具有横向突出的埋入带
公开(公告)号：US08198169B2
公开(公告)日：2012-06-12
申请号：US12974451
申请日：2010-12-21
申请人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
发明人： MaryJane Brodsky , Kangguo Cheng , Herbert L. Ho , Paul C. Parries , Kevin R. Winstel
IPC分类号： H01L21/425
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/1087
摘要： A deep trench is formed to a depth midway into a buried insulator layer of a semiconductor-on-insulator (SOI) substrate. A top semiconductor layer is laterally recessed by an isotropic etch that is selective to the buried insulator layer. The deep trench is then etched below a bottom surface of the buried insulator layer. Ion implantation is performed at an angle into the deep trench to dope the sidewalls of the deep trench beneath the buried insulator layer, while the laterally recessed sidewalls of the top semiconductor layer are not implanted with dopant ions. A node dielectric and trench fill materials are deposited into the deep trench. A buried strap has an upper buried strap sidewall that is offset from a lower buried strap sidewall and a deep trench sidewall.
摘要翻译：深沟槽形成在绝缘体上半导体（SOI）衬底的埋入绝缘体层的中间的深度处。顶部半导体层通过对掩埋绝缘体层有选择性的各向同性蚀刻而横向凹陷。然后将深沟槽蚀刻在掩埋绝缘体层的底表面下方。离子注入以一定角度进入深沟槽以掺杂隐埋绝缘体层下面的深沟槽的侧壁，而顶部半导体层的侧向凹入的侧壁不注入掺杂离子。节点电介质和沟槽填充材料沉积到深沟槽中。掩埋带具有从下埋置带侧壁和深沟槽侧壁偏移的上掩埋带侧壁。

95. 发明申请

US20120112279A1 CONTACTS FOR FET DEVICES 有权
标题翻译： FET器件的接触
公开(公告)号：US20120112279A1
公开(公告)日：2012-05-10
申请号：US12941042
申请日：2010-11-06
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
IPC分类号： H01L29/772 , H01L29/45 , H01L21/28
CPC分类号： H01L29/41733 , H01L21/28518 , H01L23/485 , H01L29/665 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： A method for contacting an FET device is disclosed. The method includes vertically recessing the device isolation, which exposes a sidewall surface on both the source and the drain. Next, silicidation is performed, resulting in a silicide layer covering both the top surface and the sidewall surface of the source and the drain. Next, metallic contacts are applied in such manner that they engage the silicide layer on both its top and on its sidewall surface. A device characterized as being an FET device structure with enlarged contact areas is also disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide on its top surface and on its sidewall surface.
摘要翻译：公开了一种接触FET器件的方法。该方法包括垂直凹陷器件隔离，其暴露源极和漏极两侧的侧壁表面。接下来，进行硅化，得到覆盖源极和漏极的顶表面和侧壁表面的硅化物层。接下来，以这样的方式施加金属触点，使得它们在其顶部和侧壁表面上接合硅化物层。还公开了一种特征在于具有扩大的接触面积的FET器件结构的器件。该装置具有垂直凹入的隔离，从而在源极和漏极两者上具有暴露的侧壁表面。硅化物层覆盖源极和漏极的顶表面和侧壁表面。与设备的金属接触件在其顶表面和其侧壁表面上接合硅化物。

96. 发明申请

US20120068267A1 STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES 有权
公开(公告)号：US20120068267A1
公开(公告)日：2012-03-22
申请号：US12886881
申请日：2010-09-21
申请人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Katherine L. Saenger
发明人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Katherine L. Saenger
IPC分类号： H01L29/786 , H01L21/762
CPC分类号： H01L21/84 , H01L21/823807
摘要： Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.

97. 发明授权

US08138543B2 Hybrid FinFET/planar SOI FETs 有权
标题翻译：混合FinFET /平面SOI FET
公开(公告)号：US08138543B2
公开(公告)日：2012-03-20
申请号：US12621460
申请日：2009-11-18
申请人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
IPC分类号： H01L27/01
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823878 , H01L27/1211 , H01L29/785
摘要： A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the planar PFET device penetrating through the SOI and abutting the insulator. Each of the three different kinds of devices contain a high-k gate dielectric layer and a mid-gap gate metal layer, each containing an identical high-k material and an identical mid-gap metal. Each of the three different kinds of devices have an individually optimized threshold value. A method for fabricating a circuit structure is also disclosed, which method involves defining portions in SOI respectively for three different kinds of devices: for a planar NFET device, for a planar PFET device, and for a FinFET device. The method also includes depositing in common a high-k gate dielectric layer and a mid-gap gate metal layer, and using workfunction modifying layers to individually adjust thresholds for the various kinds of devices.
摘要翻译：公开了一种电路结构，其包含绝缘体上硅层（SOI）中的三种不同类型的器件中的至少一种：平面NFET器件，平面PFET器件和FinFET器件。沟槽隔离围绕平面NFET器件，并且平面PFET器件穿透SOI并邻接绝缘体。三种不同类型的器件中的每一种都包含高k栅极电介质层和中间间隙栅极金属层，每个包含相同的高k材料和相同的中间间隙金属。三种不同类型的设备中的每一种具有单独优化的阈值。还公开了一种用于制造电路结构的方法，该方法包括为三种不同类型的器件分别定义SOI中的部分：对于平面NFET器件，用于平面PFET器件和FinFET器件。该方法还包括共同沉积高k栅极电介质层和中间间隙栅极金属层，并且使用功函数修改层来单独调节各种器件的阈值。

98. 发明申请

US20120061759A1 Extremely Thin Semiconductor-on-Insulator (ETSOI) FET Having a Stair-Shape Raised Source/Drain and a Method of Forming the Same 有权
标题翻译：极薄的绝缘体上半导体（ETSOI）FET，具有阶梯式引出源/漏极及其形成方法
公开(公告)号：US20120061759A1
公开(公告)日：2012-03-15
申请号：US12882490
申请日：2010-09-15
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
IPC分类号： H01L29/786 , H01L21/782
CPC分类号： H01L29/78654 , H01L29/66628 , H01L29/66772
摘要： A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S/D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S/D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S/D and the extension. A method of forming the aforementioned MOSFET device is also provided.
摘要翻译：在具有厚度范围为3nm至20nm的半导体层的绝缘体上半导体（SOI）衬底的顶部上形成MOSFET器件。在SOI衬底的顶部上形成阶梯形凸起的延伸部，凸起的源极区域和凸起的漏极区域（S / D）。更薄的凸起的延伸区域邻近薄的栅极侧壁间隔物，降低延伸电阻而不显着增加寄生电阻。单个外延生长优选同时形成更薄的凸起延伸和较高的凸起S / D，从而降低制造成本以及升高的S / D与延伸部之间的接触电阻。还提供了形成上述MOSFET器件的方法。

99. 发明申请

US20120049284A1 Same-Chip Multicharacteristic Semiconductor Structures 有权
标题翻译：同芯多特征半导体结构
公开(公告)号：US20120049284A1
公开(公告)日：2012-03-01
申请号：US12861976
申请日：2010-08-24
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L27/1211 , H01L27/1203
摘要： In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth.
摘要翻译：在一个示例性实施例中，半导体结构包括：绝缘体上半导体衬底，具有覆盖绝缘层的顶部半导体层，绝缘层覆盖在底部衬底层上; 至少一个第一装置至少部分地覆盖并设置在顶部半导体层的第一部分上，其中第一部分具有第一厚度，第一宽度和第一深度; 以及至少一个第二装置，其至少部分地覆盖并设置在顶部半导体层的第二部分上，其中第二部分具有第二厚度，第二宽度和第二深度，其中以下至少一个成立：第一厚度大于第二厚度，第一宽度大于第二宽度，第一深度大于第二深度。

100. 发明授权

US08124470B1 Strained thin body semiconductor-on-insulator substrate and device 有权
标题翻译：应变薄体绝缘体上半导体衬底和器件
公开(公告)号：US08124470B1
公开(公告)日：2012-02-28
申请号：US12892950
申请日：2010-09-29
申请人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/76283 , H01L29/66772 , H01L29/7842 , H01L29/7847 , H01L29/78603
摘要： A method of forming a strained, semiconductor-on-insulator substrate includes forming a second semiconductor layer on a first semiconductor substrate. The second semiconductor is lattice matched to the first semiconductor substrate such that the second semiconductor layer is subjected to a first directional stress. An active device semiconductor layer is formed over the second semiconductor layer such that the active device semiconductor layer is initially in a relaxed state. One or more trench isolation structures are formed through the active device layer and through the second semiconductor layer so as to relax the second semiconductor layer below the active device layer and impart a second directional stress on the active device layer opposite the first directional stress.
摘要翻译：形成应变绝缘体上半导体衬底的方法包括在第一半导体衬底上形成第二半导体层。第二半导体与第一半导体衬底晶格匹配，使得第二半导体层经受第一定向应力。在第二半导体层上形成有源器件半导体层，使得有源器件半导体层初始处于松弛状态。通过有源器件层和通过第二半导体层形成一个或多个沟槽隔离结构，以便使有源器件层下方的第二半导体层松弛，并在与第一方向应力相反的有源器件层上施加第二方向应力。

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