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91. 发明授权

US08116140B2 Saw-shaped multi-pulse programming for program noise reduction in memory 有权
标题翻译：用于程序降噪存储器的锯形多脉冲编程
公开(公告)号：US08116140B2
公开(公告)日：2012-02-14
申请号：US12757399
申请日：2010-04-09
申请人： Yingda Dong , Yupin K. Fong , Gerrit Jan Hemink
发明人： Yingda Dong , Yupin K. Fong , Gerrit Jan Hemink
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C2211/5621 , G11C2211/5622
摘要： In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which is above the initial level. One or more subsequent sub-pulses of the set can step up from an intermediate level to a peak level, and then step back down to an intermediate level. A last sub-pulse of the set can step up from an intermediate level to a peak level, and then step back down to the initial level. A verify operation is performed after the set of sub-pulses. The number of sub-pulses per set can decrease in successive sets until a solitary pulse is applied toward the end of a programming operation.
摘要翻译：在存储器系统中，编程波形通过使用具有锯齿形状的多个相邻子脉冲的集合来减少编程噪声。在一组中，初始子脉冲从初始电平（例如0V）升高到峰值电平，然后降至高于初始电平的中间电平。该集合的一个或多个后续子脉冲可以从中间电平升高到峰值电平，然后降低到中间电平。集合的最后一个子脉冲可以从中间电平升高到峰值电平，然后降低到初始电平。在子脉冲组之后执行验证操作。每组的子脉冲数可以在连续的集合中减小，直到在编程操作结束时施加孤立脉冲。

92. 发明授权

US08081519B2 Adaptive erase and soft programming for memory 有权
标题翻译：存储器的自适应擦除和软编程
公开(公告)号：US08081519B2
公开(公告)日：2011-12-20
申请号：US12899403
申请日：2010-10-06
申请人： Shih-Chung Lee , Gerrit Jan Hemink
发明人： Shih-Chung Lee , Gerrit Jan Hemink
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/16 , G11C16/3404
摘要： An erase sequence of a non-volatile storage device includes an erase operation followed by a soft programming operation. The erase operation applies one or more erase pulses to the storage elements, e.g., via a substrate, until an erase verify level is satisfied. The number of erase pulses is tracked and recorded as an indicia of the number of programming-erase cycles which the storage device has experienced. The soft programming operation applies soft programming pulses to the storage elements until a soft programming verify level is satisfied. Based on the number of erase pulses, the soft programming operation time is shortened by skipping verify operations for a specific number of initial soft programming pulses which is a function of the number of erase pulses. Also, a characteristic of the soft programming operation can be optimized, such as starting amplitude, step size or pulse duration.
摘要翻译：非易失性存储设备的擦除序列包括随后进行软编程操作的擦除操作。擦除操作例如经由衬底将一个或多个擦除脉冲施加到存储元件，直到满足擦除验证电平。跟踪和记录擦除脉冲的数量作为存储设备经历的编程擦除周期数的标记。软编程操作将软编程脉冲应用于存储元件，直到满足软编程验证电平。基于擦除脉冲的数量，通过跳过针对擦除脉冲数的函数的特定数量的初始软编程脉冲的验证操作来缩短软编程操作时间。此外，可以优化软编程操作的特性，例如起始幅度，步长或脉冲持续时间。

93. 发明授权

US08054691B2 Detecting the completion of programming for non-volatile storage 有权
标题翻译：检测完成非易失性存储的编程
公开(公告)号：US08054691B2
公开(公告)日：2011-11-08
申请号：US12492421
申请日：2009-06-26
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454
摘要： A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when all non-volatile storage elements have reached their target level or when the number of non-volatile storage elements that have not reached their target level is less than a number or memory cells that can be corrected using an error correction process during a read operation (or other operation). The number of non-volatile storage elements that have not reached their target level can be estimated by counting the number of non-volatile storage elements that have not reached a condition that is different (e.g., lower) than the target level.
摘要翻译：对一组非易失性存储元件进行编程处理以便存储数据。在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标条件以存储适当的数据。当所有非易失性存储元件已经达到其目标电平时或当尚未达到其目标电平的非易失性存储元件的数量小于可以使用纠错过程进行校正的数量或存储器单元时，可以停止编程在读取操作期间（或其他操作）。尚未达到其目标水平的非易失性存储元件的数量可以通过对尚未达到不同于目标水平的条件（例如，较低）的非易失性存储元件的数量进行计数来估计。

94. 发明授权

US08045375B2 Programming non-volatile memory with high resolution variable initial programming pulse 有权
标题翻译：用高分辨率可编程初始编程脉冲编程非易失性存储器
公开(公告)号：US08045375B2
公开(公告)日：2011-10-25
申请号：US12427013
申请日：2009-04-21
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3468 , G11C16/3486 , G11C2211/5621 , G11C2211/5648
摘要： Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the programming processes include identifying a program pulse associated with achieving a particular result for a respective programming process and performing one or more sensing operations at one or more alternative results for the non-volatile storage elements. Subsequent programming process are adjusted based on a first alternative result and the identification of the program pulse if the one or more sensing operations determined that greater than a predetermined number of non-volatile storage elements achieved the first alternative result. Subsequent programming process are adjusted based on the identification of the program pulse if the one or more sensing operations determined that less than a required number of non-volatile storage elements achieved any of the alternative results.
摘要翻译：对多个非易失性存储元件执行多个编程处理。编程过程中的每一个都使用编程脉冲来操作至少一个非易失性存储元件的子集到相应的目标条件集合。编程过程的至少一个子集包括识别与实现相应编程处理的特定结果相关联的编程脉冲，并且以非易失性存储元件的一个或多个替代结果执行一个或多个感测操作。如果一个或多个感测操作确定大于预定数量的非易失性存储元件实现了第一替代结果，则基于第一替代结果和编程脉冲的识别来调整后续编程处理。如果一个或多个感测操作确定小于所需数量的非易失性存储元件实现任何替代结果，则基于编程脉冲的识别来调整后续编程处理。

95. 发明申请

US20110151636A1 Method For Angular Doping Of Source And Drain Regions For Odd And Even NAND Blocks 有权
标题翻译：用于奇数和甚至NAND块的源极和漏极区域的掺杂方法
公开(公告)号：US20110151636A1
公开(公告)日：2011-06-23
申请号：US13024663
申请日：2011-02-10
申请人： Gerrit Jan Hemink , Shinji Sato
发明人： Gerrit Jan Hemink , Shinji Sato
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/115 , H01L27/11524 , H01L29/66825 , H01L29/7885
摘要： A method for creating NAND flash memory. Source implantations are performed at a first implantation angle to areas between stacked gate structures of a NAND string. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The source implantation can include n-type and p-type materials implanted under different angles, and the drain implantation can include n-type and p-type materials implanted under different angles. Or, the source implantation can include multiple n-type implantations under different angles, and the drain implantation can include multiple n-type implantations under different angles.
摘要翻译：一种用于创建NAND闪存的方法。以与NAND串的堆叠栅极结构之间的区域的第一注入角度执行源注入。排水注入以与叠置的栅极结构之间的区域的第二注入角度进行。源植入可以包括以不同角度注入的n型和p型材料，并且漏极注入可以包括以不同角度注入的n型和p型材料。或者，源植入可以包括在不同角度下的多个n型注入，并且漏极注入可以包括在不同角度下的多个n型注入。

96. 发明申请

US20110134699A1 APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB 有权
标题翻译：减少程序干扰的影响的装置
公开(公告)号：US20110134699A1
公开(公告)日：2011-06-09
申请号：US13025126
申请日：2011-02-10
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C16/10
CPC分类号： G11C16/3418 , G11C16/3427
摘要： The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.
摘要翻译：将在程序操作期间将未编程（或禁止的）非易失性存储元件的非故意编程称为“程序干扰”。提出了一种用于编程和/或读取非易失性存储元件的系统，易失性存储，减少程序干扰的影响。在一个实施例中，在编程过程期间，对于特定字线（或存储元件的其他分组）使用不同的验证电平。在另一个实施例中，在读取过程期间，不同的比较级别用于特定单词（或存储单元的其他分组）。

97. 发明申请

US20110134693A1 APPARATUS FOR REDUCING THE IMPACT OF PROGRAM DISTURB 有权
公开(公告)号：US20110134693A1
公开(公告)日：2011-06-09
申请号：US13025123
申请日：2011-02-10
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.

98. 发明申请

US20110044102A1 SELECTIVE MEMORY CELL PROGRAM AND ERASE 有权
标题翻译：选择性记忆细胞程序和删除
公开(公告)号：US20110044102A1
公开(公告)日：2011-02-24
申请号：US12544113
申请日：2009-08-19
申请人： Yingda Dong , Tien-chien Kuo , Gerrit Jan Hemink
发明人： Yingda Dong , Tien-chien Kuo , Gerrit Jan Hemink
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/30 , G11C16/3418 , G11C2211/5641
摘要： Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.
摘要翻译：本文公开了用于编程存储器阵列以实现高编程/擦除周期耐久性的技术。在某些方面，只有选择的字线（WL）被编程，其他WL保持未编程。作为示例，只有偶数字线被编程，剩余的未编程的奇数WL。在所有偶数字线被编程并且数据块要用新数据编程之后，块被擦除。之后，只有奇数字线被编程。数据可以被传送到在擦除之前存储多个存储单元的位的块。在一个方面，数据以棋盘格式编程，其中编程了一些存储器单元，而其他存储器单元未被编程。之后，在擦除数据之后，棋盘格图案的以前未编程的部分被编程为剩余的单元未编程。

99. 发明授权

US07843739B2 System for verifying non-volatile storage using different voltages 有权
标题翻译：使用不同电压验证非易失性存储的系统
公开(公告)号：US07843739B2
公开(公告)日：2010-11-30
申请号：US12203544
申请日：2008-09-03
申请人： Gerrit Jan Hemink
发明人： Gerrit Jan Hemink
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5642 , G11C16/3418 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： When performing a data sensing operation, including a verify operation during programming of non-volatile storage elements (or, in some cases, during a read operation after programming), a first voltage is used for unselected word lines that have been subjected to a programming operation and a second voltage is used for unselected word lines that have not been subjected to a programming operation. In some embodiments, the second voltage is lower than the first voltage.
摘要翻译：当执行数据检测操作时，包括在编程非易失性存储元件期间（或在某些情况下，在编程之后的读取操作期间）中的验证操作，第一电压被用于已经经过编程的未被选择的字线对未经过编程操作的未选字线使用第二电压。在一些实施例中，第二电压低于第一电压。

100. 发明申请

US20100297823A1 METHOD FOR ANGULAR DOPING OF SOURCE AND DRAIN REGIONS FOR ODD AND EVEN NAND BLOCKS 有权
标题翻译：用于ODD和即使NAND块的源和漏区的角度去除的方法
公开(公告)号：US20100297823A1
公开(公告)日：2010-11-25
申请号：US12835468
申请日：2010-07-13
申请人： Gerrit Jan Hemink , Shinji Sato
发明人： Gerrit Jan Hemink , Shinji Sato
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/115 , H01L27/11524 , H01L29/66825 , H01L29/7885
摘要： Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped regions of a first conductivity type in the substrate on drain sides of the stacked gate structures. The source implantations create higher doped regions of the first conductivity type in the substrate on source sides of the stacked gate structures.
摘要翻译：在衬底上产生用于NAND串的堆叠栅极结构。以与堆叠的栅极结构之间的区域的第一注入角度进行源植入。排水注入以与叠置的栅极结构之间的区域的第二注入角度进行。漏极注入在堆叠栅极结构的漏极侧的衬底中产生第一导电类型的较低掺杂区域。源极注入在层叠栅极结构的源极侧的衬底中产生第一导电类型的较高掺杂区域。

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