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1. 发明授权

US08804430B2 Selected word line dependent select gate diffusion region voltage during programming 有权
标题翻译：选择字线依赖选择栅扩散区电压编程
公开(公告)号：US08804430B2
公开(公告)日：2014-08-12
申请号：US13430494
申请日：2012-03-26
申请人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
发明人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
IPC分类号： G11C11/34 , G11C16/04 , G11C16/10 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/04 , G11C16/06 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于为编程选择的字线的位置。应用所选字线相关程序条件可能会减少或消除程序干扰。施加到公共源极线的电压可以取决于被选择用于编程的字线的位置。这可以防止或减少穿通传导，这可以防止或减少程序干扰。施加到未选择NAND串的位线的电压可能取决于选择用于编程的字线的位置。这可以防止或减少穿透传导。

2. 发明申请

US20110205823A1 Non-Volatile Storage With Temperature Compensation Based On Neighbor State Information 有权
标题翻译：基于邻居状态信息的温度补偿非易失性存储
公开(公告)号：US20110205823A1
公开(公告)日：2011-08-25
申请号：US12708699
申请日：2010-02-19
申请人： Gerrit Jan Hemink , Shinji Sato
发明人： Gerrit Jan Hemink , Shinji Sato
IPC分类号： G11C7/04
CPC分类号： G11C16/26 , G11C7/04 , G11C11/5642
摘要： Data is programmed into and read from a set of target memory cells. When reading the data, temperature compensation is provided. The temperature compensation is based on temperature information and the state of one or more neighbor memory cells. In one embodiment, when data is read from set of target memory cells, the system senses the current temperature and determines the differences in temperature between the current temperature and the temperature at the time the data was programmed. If the difference in temperature is greater than a threshold, then the process of reading the data includes providing temperature compensation based on temperature information and neighbor state information. In one alternative, the decision to provide the temperature compensation can be triggered by conditions other than a temperature differential.
摘要翻译：数据被编程到一组目标存储器单元中并从其读取。读取数据时，提供温度补偿。温度补偿基于温度信息和一个或多个相邻存储单元的状态。在一个实施例中，当从目标存储器单元的集合读取数据时，系统感测当前温度并确定当前温度与数据编程时的温度之间的温度差。如果温度差大于阈值，则读取数据的过程包括基于温度信息和邻近状态信息提供温度补偿。在一个替代方案中，提供温度补偿的决定可以由温差以外的条件触发。

3. 发明授权

US07902031B2 Method for angular doping of source and drain regions for odd and even NAND blocks 有权
标题翻译：用于奇数和非NAND块的源极和漏极区域的角掺杂的方法
公开(公告)号：US07902031B2
公开(公告)日：2011-03-08
申请号：US12835468
申请日：2010-07-13
申请人： Gerrit Jan Hemink , Shinji Sato
发明人： Gerrit Jan Hemink , Shinji Sato
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/115 , H01L27/11524 , H01L29/66825 , H01L29/7885
摘要： A method for creating NAND flash memory. Source implantations are performed at a first implantation angle to areas between stacked gate structures of a NAND string. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The implantations can dope a source line area while not doping a bit line contact area, and providing an additional implantation for the bit line contact area, or dope the bit line contact area while not doping the source line area, followed by an additional implantation for the source line area, or dope neither the source line area nor the bit line contact area, followed by additional implantations for the source line area and the bit line contact area.
摘要翻译：一种用于创建NAND闪存的方法。以与NAND串的堆叠栅极结构之间的区域的第一注入角度执行源注入。排水注入以与叠置的栅极结构之间的区域的第二注入角度进行。注入可以掺杂源极区域而不掺杂位线接触区域，并且为位线接触区域提供额外的注入，或掺杂位线接触区域而不掺杂源极区域，然后进行额外的注入源极区域，或者既不影响源极线区域也不掺杂位线接触区域，随后对源极线区域和位线接触区域进行额外的注入。

4. 发明授权

US07719902B2 Enhanced bit-line pre-charge scheme for increasing channel boosting in non-volatile storage 有权
标题翻译：增强的位线预充电方案，用于在非易失性存储器中增加通道增强
公开(公告)号：US07719902B2
公开(公告)日：2010-05-18
申请号：US12126375
申请日：2008-05-23
申请人： Yingda Dong , Man L. Mui , Jeffrey W. Lutze , Shinji Sato , Gerrit Jan Hemink
发明人： Yingda Dong , Man L. Mui , Jeffrey W. Lutze , Shinji Sato , Gerrit Jan Hemink
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/32 , G11C16/3418 , G11C16/3427
摘要： Channel boosting is improved in non-volatile storage to reduce program disturb. A pre-charge module voltage source is used to pre-charge bit lines during a programming operation. The pre-charge module voltage source is coupled to a substrate channel via the bit lines to boost the channel. An additional source of boosting is provided by electromagnetically coupling a voltage from a conductive element to the bit lines and the channel. To achieve this, the bit lines and the channel are allowed to float together by disconnecting the bit lines from the voltage sources. The conductive element can be a source line, power supply line or substrate body, for instance, which receives an increasing voltage during the pre-charging and is proximate to the bit lines.
摘要翻译：在非易失性存储器中改善通道增强以减少程序干扰。预充电模块电压源用于在编程操作期间对位线进行预充电。预充电模块电压源通过位线耦合到衬底通道以升高通道。通过将来自导电元件的电压电磁耦合到位线和通道来提供额外的升压源。为了实现这一点，通过将位线与电压源断开来允许位线和通道浮动在一起。导电元件可以是例如在预充电期间接收增加的电压并且靠近位线的源极线，电源线或衬底主体。

5. 发明授权

US07534690B2 Non-volatile memory with asymmetrical doping profile 有权
标题翻译：具有不对称掺杂特性的非易失性存储器
公开(公告)号：US07534690B2
公开(公告)日：2009-05-19
申请号：US11469281
申请日：2006-08-31
申请人： Gerrit Jan Hemink , Shinji Sato
发明人： Gerrit Jan Hemink , Shinji Sato
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/115 , H01L27/11524 , H01L29/66825 , H01L29/7885
摘要： Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped regions of a first conductivity type in the substrate on drain sides of the stacked gate structures. The source implantations create higher doped regions of the first conductivity type in the substrate on source sides of the stacked gate structures.
摘要翻译：在衬底上产生用于NAND串的堆叠栅极结构。以与堆叠的栅极结构之间的区域的第一注入角度进行源植入。排水注入以与叠置的栅极结构之间的区域的第二注入角度进行。漏极注入在堆叠栅极结构的漏极侧的衬底中产生第一导电类型的较低掺杂区域。源极注入在层叠栅极结构的源极侧的衬底中产生第一导电类型的较高掺杂区域。

6. 发明授权

US07294882B2 Non-volatile memory with asymmetrical doping profile 有权
标题翻译：具有不对称掺杂特性的非易失性存储器
公开(公告)号：US07294882B2
公开(公告)日：2007-11-13
申请号：US10952689
申请日：2004-09-28
申请人： Gerrit Jan Hemink , Shinji Sato
发明人： Gerrit Jan Hemink , Shinji Sato
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/115 , H01L27/11524 , H01L29/66825 , H01L29/7885
摘要： Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped regions of a first conductivity type in the substrate on drain sides of the stacked gate structures. The source implantations create higher doped regions of the first conductivity type in the substrate on source sides of the stacked gate structures.
摘要翻译：在衬底上产生用于NAND串的堆叠栅极结构。以与堆叠的栅极结构之间的区域的第一注入角度进行源植入。排水注入以与叠置的栅极结构之间的区域的第二注入角度进行。漏极注入在堆叠栅极结构的漏极侧的衬底中产生第一导电类型的较低掺杂区域。源极注入在层叠栅极结构的源极侧的衬底中产生第一导电类型的较高掺杂区域。

7. 发明申请

US20130250690A1 SELECTED WORD LINE DEPENDENT SELECT GATE VOLTAGE DURING PROGRAM 有权
标题翻译：在程序期间选择的字线相关选择门电压
公开(公告)号：US20130250690A1
公开(公告)日：2013-09-26
申请号：US13430502
申请日：2012-03-26
申请人： Chun-Hung Lai , Deepanshu Dutta , Shinji Sato , Gerrit Jan Hemink
发明人： Chun-Hung Lai , Deepanshu Dutta , Shinji Sato , Gerrit Jan Hemink
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于选择用于编程的字线的位置，这可以减少或消除程序干扰。施加到NAND串的选择晶体管的栅极的电压可以取决于所选字线的位置。这可以是源极侧或漏极侧选择晶体管。这可能会阻止或减少由于DIBL而导致的程序干扰。这也可以防止或减少由于GIDL可能导致的程序干扰。当编程至少一些字线时，负偏压可以施加到源极侧选择晶体管的栅极。在一个实施例中，当编程逐渐增加的字线时，逐渐降低的电压用于漏极侧选择晶体管的栅极。

8. 发明申请

US20130250689A1 SELECTED WORD LINE DEPENDENT SELECT GATE DIFFUSION REGION VOLTAGE DURING PROGRAMMING 有权
标题翻译：在编程期间选择的字线相关选择门限扩展区域电压
公开(公告)号：US20130250689A1
公开(公告)日：2013-09-26
申请号：US13430494
申请日：2012-03-26
申请人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
发明人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/04 , G11C16/06 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于为编程选择的字线的位置。应用所选字线相关程序条件可能会减少或消除程序干扰。施加到公共源极线的电压可以取决于被选择用于编程的字线的位置。这可以防止或减少穿通传导，这可以防止或减少程序干扰。施加到未选择NAND串的位线的电压可能取决于选择用于编程的字线的位置。这可以防止或减少穿透传导。

9. 发明申请

US20090290429A1 ENHANCED BIT-LINE PRE-CHARGE SCHEME FOR INCREASING CHANNEL BOOSTING IN NON-VOLATILE STORAGE 有权
标题翻译：增强非易失性存储器中的通道增强的双线预先计费方案
公开(公告)号：US20090290429A1
公开(公告)日：2009-11-26
申请号：US12126375
申请日：2008-05-23
申请人： Yingda Dong , Man L. Mui , Jeffrey W. Lutze , Shinji Sato , Gerrit Jan Hemink
发明人： Yingda Dong , Man L. Mui , Jeffrey W. Lutze , Shinji Sato , Gerrit Jan Hemink
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/32 , G11C16/3418 , G11C16/3427
摘要： Channel boosting is improved in non-volatile storage to reduce program disturb. A pre-charge module voltage source is used to pre-charge bit lines during a programming operation. The pre-charge module voltage source is coupled to a substrate channel via the bit lines to boost the channel. An additional source of boosting is provided by electromagnetically coupling a voltage from a conductive element to the bit lines and the channel. To achieve this, the bit lines and the channel are allowed to float together by disconnecting the bit lines from the voltage sources. The conductive element can be a source line, power supply line or substrate body, for instance, which receives an increasing voltage during the pre-charging and is proximate to the bit lines.
摘要翻译：在非易失性存储器中改善通道增强以减少程序干扰。预充电模块电压源用于在编程操作期间对位线进行预充电。预充电模块电压源通过位线耦合到衬底通道以升高通道。通过将来自导电元件的电压电磁耦合到位线和通道来提供额外的升压源。为了实现这一点，通过将位线与电压源断开来允许位线和通道浮动在一起。导电元件可以是例如在预充电期间接收增加的电压并且靠近位线的源极线，电源线或衬底主体。

10. 发明申请

US20090233412A1 METHOD FOR ANGULAR DOPING OF SOURCE AND DRAIN REGIONS FOR ODD AND EVEN NAND BLOCKS 有权
标题翻译：用于ODD和即使NAND块的源和漏区的角度去除的方法
公开(公告)号：US20090233412A1
公开(公告)日：2009-09-17
申请号：US12419637
申请日：2009-04-07
申请人： Gerrit Jan Hemink , Shinji Sato
发明人： Gerrit Jan Hemink , Shinji Sato
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/115 , H01L27/11524 , H01L29/66825 , H01L29/7885
摘要： Stacked gate structures for a NAND string are created on a substrate. Source implantations are performed at a first implantation angle to areas between the stacked gate structures. Drain implantations are performed at a second implantation angle to areas between the stacked gate structures. The drain implantations create lower doped regions of a first conductivity type in the substrate on drain sides of the stacked gate structures. The source implantations create higher doped regions of the first conductivity type in the substrate on source sides of the stacked gate structures.
摘要翻译：在衬底上产生用于NAND串的堆叠栅极结构。以与堆叠的栅极结构之间的区域的第一注入角度进行源植入。排水注入以与叠置的栅极结构之间的区域的第二注入角度进行。漏极注入在堆叠栅极结构的漏极侧的衬底中产生第一导电类型的较低掺杂区域。源极注入在层叠栅极结构的源极侧的衬底中产生第一导电类型的较高掺杂区域。

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