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1. 发明授权

US08804430B2 Selected word line dependent select gate diffusion region voltage during programming 有权
标题翻译：选择字线依赖选择栅扩散区电压编程
公开(公告)号：US08804430B2
公开(公告)日：2014-08-12
申请号：US13430494
申请日：2012-03-26
申请人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
发明人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
IPC分类号： G11C11/34 , G11C16/04 , G11C16/10 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/04 , G11C16/06 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于为编程选择的字线的位置。应用所选字线相关程序条件可能会减少或消除程序干扰。施加到公共源极线的电压可以取决于被选择用于编程的字线的位置。这可以防止或减少穿通传导，这可以防止或减少程序干扰。施加到未选择NAND串的位线的电压可能取决于选择用于编程的字线的位置。这可以防止或减少穿透传导。

2. 发明申请

US20110019483A1 ADAPTIVE ERASE AND SOFT PROGRAMMING FOR MEMORY 有权
标题翻译：自适应删除和软件编程存储器
公开(公告)号：US20110019483A1
公开(公告)日：2011-01-27
申请号：US12899403
申请日：2010-10-06
申请人： Shih-Chung Lee , Gerrit Jan Hemink
发明人： Shih-Chung Lee , Gerrit Jan Hemink
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/16 , G11C16/3404
摘要： An erase sequence of a non-volatile storage device includes an erase operation followed by a soft programming operation. The erase operation applies one or more erase pulses to the storage elements, e.g., via a substrate, until an erase verify level is satisfied. The number of erase pulses is tracked and recorded as an indicia of the number of programming-erase cycles which the storage device has experienced. The soft programming operation applies soft programming pulses to the storage elements until a soft programming verify level is satisfied. Based on the number of erase pulses, the soft programming operation time is shortened by skipping verify operations for a specific number of initial soft programming pulses which is a function of the number of erase pulses. Also, a characteristic of the soft programming operation can be optimized, such as starting amplitude, step size or pulse duration.
摘要翻译：非易失性存储设备的擦除序列包括随后进行软编程操作的擦除操作。擦除操作例如经由衬底将一个或多个擦除脉冲施加到存储元件，直到满足擦除验证电平。跟踪和记录擦除脉冲的数量作为存储设备经历的编程擦除周期数的标记。软编程操作将软编程脉冲应用于存储元件，直到满足软编程验证电平。基于擦除脉冲的数量，通过跳过针对擦除脉冲数的函数的特定数量的初始软编程脉冲的验证操作来缩短软编程操作时间。此外，可以优化软编程操作的特性，例如起始幅度，步长或脉冲持续时间。

3. 发明授权

US07839690B2 Adaptive erase and soft programming for memory 有权
标题翻译：存储器的自适应擦除和软编程
公开(公告)号：US07839690B2
公开(公告)日：2010-11-23
申请号：US12332646
申请日：2008-12-11
申请人： Shih-Chung Lee , Gerrit Jan Hemink
发明人： Shih-Chung Lee , Gerrit Jan Hemink
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5635 , G11C16/16 , G11C16/3404
摘要： An erase sequence of a non-volatile storage device includes an erase operation followed by a soft programming operation. The erase operation applies one or more erase pulses to the storage elements, e.g., via a substrate, until an erase verify level is satisfied. The number of erase pulses is tracked and recorded as an indicia of the number of programming-erase cycles which the storage device has experienced. The soft programming operation applies soft programming pulses to the storage elements until a soft programming verify level is satisfied. Based on the number of erase pulses, the soft programming operation time is shortened by skipping verify operations for a specific number of initial soft programming pulses which is a function of the number of erase pulses. Also, a characteristic of the soft programming operation can be optimized, such as starting amplitude, step size or pulse duration.
摘要翻译：非易失性存储设备的擦除序列包括随后进行软编程操作的擦除操作。擦除操作例如经由衬底将一个或多个擦除脉冲施加到存储元件，直到满足擦除验证电平。跟踪和记录擦除脉冲的数量作为存储设备经历的编程擦除周期数的标记。软编程操作将软编程脉冲应用于存储元件，直到满足软编程验证电平。基于擦除脉冲的数量，通过跳过针对擦除脉冲数的函数的特定数量的初始软编程脉冲的验证操作来缩短软编程操作时间。此外，可以优化软编程操作的特性，例如起始幅度，步长或脉冲持续时间。

4. 发明授权

US07460404B1 Boosting for non-volatile storage using channel isolation switching 有权
标题翻译：使用通道隔离切换提升非易失性存储
公开(公告)号：US07460404B1
公开(公告)日：2008-12-02
申请号：US11745082
申请日：2007-05-07
申请人： Yingda Dong , Jeffrey W. Lutze , Shih-Chung Lee , Gerrit Jan Hemink , Ken Oowada
发明人： Yingda Dong , Jeffrey W. Lutze , Shih-Chung Lee , Gerrit Jan Hemink , Ken Oowada
IPC分类号： G11C16/00
CPC分类号： G11C16/12 , G11C16/0483
摘要： Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.
摘要翻译：在非易失性存储器中通过防止所选择的NAND串中的源极升压来减少编程干扰。使用包括隔离字线的自增强模式。禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

5. 发明申请

US20130250689A1 SELECTED WORD LINE DEPENDENT SELECT GATE DIFFUSION REGION VOLTAGE DURING PROGRAMMING 有权
标题翻译：在编程期间选择的字线相关选择门限扩展区域电压
公开(公告)号：US20130250689A1
公开(公告)日：2013-09-26
申请号：US13430494
申请日：2012-03-26
申请人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
发明人： Chun-Hung Lai , Shinji Sato , Shih-Chung Lee , Gerrit Jan Hemink
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/04 , G11C16/06 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/1202
摘要： Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction.
摘要翻译：公开了用于操作非易失性存储器的方法和装置。一个或多个编程条件取决于为编程选择的字线的位置。应用所选字线相关程序条件可能会减少或消除程序干扰。施加到公共源极线的电压可以取决于被选择用于编程的字线的位置。这可以防止或减少穿通传导，这可以防止或减少程序干扰。施加到未选择NAND串的位线的电压可能取决于选择用于编程的字线的位置。这可以防止或减少穿透传导。

6. 发明授权

US07596031B2 Faster programming of highest multi-level state for non-volatile memory 有权
标题翻译：更快地编程用于非易失性存储器的最高多级状态
公开(公告)号：US07596031B2
公开(公告)日：2009-09-29
申请号：US11554223
申请日：2006-10-30
申请人： Gerrit Jan Hemink , Shih-Chung Lee
发明人： Gerrit Jan Hemink , Shih-Chung Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： A coarse/fine programming technique is used for programming to lower states while using a standard technique (not coarse/fine programming) for programming to the highest state(s). However, when the programming of the lower states is finished, a number of programming pulses are still needed to program the highest state. To improve the programming speed, a bigger step size and longer programming pulse can be used from the moment that the lowest states have been programmed. At the same time, the programming technique for the highest state can be changed to a coarse/fine programming technique.
摘要翻译：在使用标准技术（不是粗/精编程）来编程到最高状态时，粗/精编程技术用于编程以降低状态。然而，当下部状态的编程完成时，仍然需要多个编程脉冲来编程最高状态。为了提高编程速度，从最低状态被编程的时刻起，可以使用更大的步长和更长的编程脉冲。同时，用于最高状态的编程技术可以改变为粗/精编程技术。

7. 发明授权

US07466590B2 Self-boosting method for flash memory cells 有权
标题翻译：闪存单元的自增强方法
公开(公告)号：US07466590B2
公开(公告)日：2008-12-16
申请号：US11321955
申请日：2005-12-28
申请人： Gerrit Jan Hemink , Hironobu Nakao , Shih-Chung Lee
发明人： Gerrit Jan Hemink , Hironobu Nakao , Shih-Chung Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C16/3427
摘要： A low voltage (e.g. of the order of or one to three volts) instead of an intermediate VPASS voltage (e.g. of the order of five to ten volts) is applied to word line zero immediately adjacent to the source or drain side select gate of a flash device such as a NAND flash device and one or more additional word lines next to such word line to reduce or prevent the shifting of threshold voltage of the memory cells coupled to word line zero during the programming cycles of the different cells of the NAND strings. This may be implemented in any one of a variety of different self boosting schemes including erased areas self boosting and local self boosting schemes. In a modified erased area self boosting scheme, low voltages are applied to two or more word lines on the source side of the selected word line to reduce band-to-band tunneling and to improve the isolation between two boosted channel regions. In a modified local self boosting scheme, zero volt or low voltages are applied to two or more word lines on the source side and to two or more word lines on the drain side of the selected word line to reduce band-to-band tunneling and to improve the isolation of the channel areas coupled to the selected word line. Different intermediate boosting voltage(s) (e.g. of the order of five to ten volts) may be applied to one or more of the word lines adjacent to the selected word line (that is the word line programming the selected transistor), where the boosting voltage(s) applied to the word line(s) adjacent to the selected word line are/is different from that or those applied to other unselected word lines.
摘要翻译：代替中间VPASS电压（例如5到10伏数量级）的低电压（例如，一级或一到三伏）被施加到紧邻源极或漏极侧选择栅极的字线零点闪存器件，例如NAND闪存器件，以及在该字线旁边的一个或多个附加字线，以在NAND串的不同单元的编程周期期间减少或防止耦合到字线零的存储器单元的阈值电压偏移。这可以在各种不同的自增强方案中的任何一种中实现，包括擦除区域自增强和局部自增强方案。在修改的擦除区域自增强方案中，将低电压施加到所选字线的源极侧上的两个或更多个字线，以减少带间隧穿并改善两个增强的通道区域之间的隔离。在修改后的局部自增强方案中，将零电压或低电压施加到源极侧的两条或更多条字线和所选择的字线的漏极侧上的两条或多条字线，以减少带间隧穿和以改善耦合到所选字线的通道区域的隔离。不同的中间升压电压（例如，五到十伏数量级）可以施加到与所选字线相邻的一条或多条字线（即所选择的晶体管的字线编程），其中升压施加到与所选字线相邻的字线的电压与施加到所选字线的字线的电压不同。

8. 发明申请

US20080279007A1 BOOSTING FOR NON-VOLATILE STORAGE USING CHANNEL ISOLATION SWITCHING 有权
标题翻译：使用通道隔离开关来促进非易失性存储
公开(公告)号：US20080279007A1
公开(公告)日：2008-11-13
申请号：US11745082
申请日：2007-05-07
申请人： Yingda Dong , Jeffrey W. Lutze , Shih-Chung Lee , Gerrit Jan Hemink , Ken Oowada
发明人： Yingda Dong , Jeffrey W. Lutze , Shih-Chung Lee , Gerrit Jan Hemink , Ken Oowada
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/0483
摘要： Program disturb is reduced in non-volatile storage by preventing source side boosting in selected NAND strings. A self-boosting mode which includes an isolation word line is used. A channel area of an inhibited NAND string is boosted on a source side of the isolation word line before the channel is boosted on a drain side of the isolation word line. Further, storage elements near the isolation word line are kept in a conducting state during the source side boosting so that the source side channel is connected to the drain side channel. In this way, in selected NAND strings, source side boosting can not occur and thus program disturb due to source side boosting can be prevented. After the source side boosting, the source side channel is isolated from the drain side channel, and drain side boosting is performed.
摘要翻译：在非易失性存储器中通过防止所选择的NAND串中的源极升压来减少编程干扰。使用包括隔离字线的自增强模式。禁止的NAND串的通道区域在隔离字线的漏极侧的通道升压之前在隔离字线的源极侧被升压。此外，在源侧升压期间，隔离字线附近的存储元件保持导通状态，使得源极侧沟道连接到漏极侧沟道。以这种方式，在选择的NAND串中，不能发生源侧升压，因此可以防止由于源极侧升压而导致的编程干扰。在源侧升压之后，源侧沟道与漏极侧沟道隔离，并且进行漏极侧升压。

9. 发明申请

US20120300550A1 Ramping Pass Voltage To Enhance Channel Boost In Memory Device, With Optional Temperature Compensation 有权
标题翻译：缓存通过电压，以增强存储器件中的通道升压，具有可选的温度补偿
公开(公告)号：US20120300550A1
公开(公告)日：2012-11-29
申请号：US13113786
申请日：2011-05-23
申请人： Gerrit Jan Hemink , Shih-Chung Lee , Anubhav Khandelwal , Henry Chin , Guirong Liang , Dana Lee
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Anubhav Khandelwal , Henry Chin , Guirong Liang , Dana Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/3427 , G11C16/10
摘要： In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period in which a program pulse is applied to a selected word line. The increase can be gradual, in the form of a ramp, or step-wise. The boosting level of the first channel region can be maintained. The increase in the voltage applied to the one or more unselected word lines can vary with temperature as well. Before the program pulse time period, the voltage applied to the one or more unselected word lines can be ramped up at a faster rate for a second, adjacent channel region than for the first channel region, to help isolate the channel regions.
摘要翻译：在非易失性存储系统中，用于未选择的NAND串的一个或多个衬底沟道区在编程期间升高以抑制编程干扰。在将编程脉冲施加到所选字线的编程脉冲时间段期间，施加到与至少第一信道区域相关联的一个或多个未选择字线的电压增加。增加可以是渐进的，以斜坡的形式，或逐步的。可以维持第一通道区域的升压水平。施加到一个或多个未选择字线的电压的增加也随着温度而变化。在编程脉冲时间段之前，施加到一个或多个未选择字线的电压可以以比第一通道区域更快的速率向第二相邻通道区域上升，以帮助隔离通道区域。

10. 发明授权

US08189378B2 Reducing program disturb in non-volatile storage 有权
标题翻译：在非易失性存储中减少程序干扰
公开(公告)号：US08189378B2
公开(公告)日：2012-05-29
申请号：US11535628
申请日：2006-09-27
申请人： Gerrit Jan Hemink , Shih-Chung Lee
发明人： Gerrit Jan Hemink , Shih-Chung Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C7/1006 , G11C11/5628 , G11C16/12 , G11C16/3418 , G11C16/3427 , G11C2211/5621
摘要： A non-volatile semiconductor storage system is programmed in a manner that reduces program disturb by applying a higher boosting voltage on one or more word lines that are connected to non-volatile storage elements that may be partially programmed.
摘要翻译：非易失性半导体存储系统被编程为通过在连接到可以被部分编程的非易失性存储元件的一个或多个字线上施加更高的升压电压来减少编程干扰。

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