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91. 发明授权

US07558358B1 Method and apparatus for generating a clock signal according to an ideal frequency ratio 有权
标题翻译：用于根据理想频率比产生时钟信号的方法和装置
公开(公告)号：US07558358B1
公开(公告)日：2009-07-07
申请号：US11691964
申请日：2007-03-27
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： H03D3/24
CPC分类号： H03L7/1976 , G09G3/2096 , G09G5/006 , H03L7/235 , H03L2207/50
摘要： A method and apparatus for generating a clock signal according to an ideal frequency ratio provides flexible and reduced frequency error clock generation. A ratio control number is specified or is determined from a phase-frequency comparison of the clock signal to a timing reference. A correction factor is specified as a numerator and denominator and an error is accumulated according to the numerator and denominator of the correction factor. The ratio control number is adjusted according to the accumulated error so that an ideal ratio is maintained between the frequency of the clock signal and the frequency of the timing reference. If the ratio is determined from a phase-frequency correction, then the phase-frequency error is adjusted so that a loop filter output is corrected on average. Otherwise, the ratio control number is adjusted directly.
摘要翻译：用于根据理想频率比产生时钟信号的方法和装置提供灵活且降低的频率误差时钟产生。根据时钟信号与定时参考的相位 - 频率比较来指定比例控制编号或确定比率控制编号。校正因子被指定为分子和分母，并且根据校正因子的分子和分母累积误差。根据累积误差来调整比率控制数，使得在时钟信号的频率和定时参考的频率之间保持理想的比率。如果从相位频率校正确定该比率，则调整相位频率误差，使得平均校正环路滤波器输出。否则，直接调整比率控制编号。

92. 发明授权

US07554473B2 Control system using a nonlinear delta-sigma modulator with nonlinear process modeling 有权
标题翻译：使用非线性过程建模的非线性Δ-Σ调制器的控制系统
公开(公告)号：US07554473B2
公开(公告)日：2009-06-30
申请号：US11865032
申请日：2007-09-30
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： H03M3/00
CPC分类号： H02M1/4225 , H03M3/476 , Y02B70/126 , Y02P80/112
摘要： A control system includes a nonlinear delta-sigma modulator, and the nonlinear delta-sigma modulator includes a nonlinear process model that models a nonlinear process in a signal processing system, such as a nonlinear plant. The nonlinear delta-sigma modulator includes a feedback model that models the nonlinear process being controlled and facilitates spectral shaping to shift noise out of a baseband in a spectral domain of a response signal of the nonlinear process. In at least one embodiment, the nonlinear delta-sigma modulator is part of a control system that controls power factor correction and output voltage of a switching power converter. The control system controls the pulse width and period of a control signal to control power factor correction and the output voltage level. In at least one embodiment, the nonlinear delta-sigma modulator generates a signal to control the pulse width of the control signal.
摘要翻译：控制系统包括非线性Δ-Σ调制器，并且非线性Δ-Σ调制器包括在诸如非线性工厂的信号处理系统中对非线性处理进行建模的非线性过程模型。非线性Δ-Σ调制器包括对被控制的非线性过程进行建模的反馈模型，并且有助于频谱整形以将噪声从非线性过程的响应信号的频谱域中的基带移出。在至少一个实施例中，非线性Δ-Σ调制器是控制开关功率转换器的功率因数校正和输出电压的控制系统的一部分。控制系统控制控制信号的脉冲宽度和周期，以控制功率因数校正和输出电压电平。在至少一个实施例中，非线性Δ-Σ调制器产生一个信号来控制控制信号的脉冲宽度。

93. 发明授权

US07471340B1 Video quality adaptive variable-rate buffering method and system for stabilizing a sampled video signal 有权
标题翻译：用于稳定采样视频信号的视频质量自适应可变速率缓冲方法和系统
公开(公告)号：US07471340B1
公开(公告)日：2008-12-30
申请号：US11088447
申请日：2005-03-24
申请人： Ahsan Chowdhury , Rahul Singh , John L. Melanson , James A. Antone
发明人： Ahsan Chowdhury , Rahul Singh , John L. Melanson , James A. Antone
IPC分类号： H03M1/12 , H03L7/00 , H04N9/64
CPC分类号： H03L7/1974 , H03L7/08 , H03L7/0805 , H03L2207/50 , H04N5/12 , H04N5/213 , H04N5/765 , H04N5/85 , H04N7/0132 , H04N9/8042 , H04N9/896 , H04N21/4325 , H04N21/44004
摘要： A video quality adaptive variable-rate buffering method and system for stabilizing a sampled video signal reduces the buffer size required to compensate for line-to-line variations in an unstable video source. A video signal is sampled at a predetermined rate and decimated by a selectable decimation factor prior to buffering. By selecting different decimation factors, the effective length of the buffer is changed from short duration for stable input signals and to longer duration for unstable input signals. A video signal quality detector is employed to provide a selection input that adjusts the decimation factor and also the loop bandwidth of a clock generator that provides the output clock for the buffer, which is generated from the input signal via a phase-lock loop (PLL). The operation of the system automatically varies from highly responsive for stable video input signals to less responsive for unstable video input signals, providing improved stability in the video output.
摘要翻译：用于稳定采样视频信号的视频质量自适应可变速率缓冲方法和系统降低了补偿不稳定视频源中的线间变化所需的缓冲器大小。以预定的速率对视频信号进行采样，并在缓冲之前用可选择的抽取因子进行抽取。通过选择不同的抽取因子，缓冲器的有效长度从稳定输入信号的短持续时间改变为不稳定输入信号的持续时间。采用视频信号质量检测器来提供选择输入，其调节抽取因子以及时钟发生器的环路带宽，该时钟发生器提供缓冲器的输出时钟，该时钟发生器通过锁相环（PLL）从输入信号产生）。系统的操作自动变化，从稳定的视频输入信号的高度响应到对不稳定的视频输入信号的响应不足，提高了视频输出的稳定性。

94. 发明申请

US20080272758A1 Switching Power Converter with Switch Control Pulse Width Variability at Low Power Demand Levels 有权
标题翻译：具有开关控制的开关电源转换器低功率需求级别的脉冲宽度变化
公开(公告)号：US20080272758A1
公开(公告)日：2008-11-06
申请号：US12114130
申请日：2008-05-02
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： G05F1/575
CPC分类号： H02M1/4225 , H03M3/476 , Y02B70/126 , Y02P80/112
摘要： A power control system includes a switch mode controller to control the switching mode of a switching power converter. The switch mode controller generates a switch control signal that controls conductivity of a switch of the switching power converter. Controlling conductivity of the switch controls the switch mode of the switching power converter. The switch mode controller includes a period generator to determine a period of the switch control signal and to vary the determined period to generate a broad frequency spectrum of the switch control signal when the determined period corresponds with a frequency in at least a portion of an audible frequency band. Generating a switch control signal with a broad frequency spectrum in the audible frequency band allows the system to utilize switching frequencies in the audible frequency band.
摘要翻译：功率控制系统包括用于控制开关功率转换器的开关模式的开关模式控制器。开关模式控制器产生控制开关功率转换器的开关的电导率的开关控制信号。控制开关电导率控制开关电源转换器的开关模式。开关模式控制器包括周期发生器，用于确定开关控制信号的周期，并且当所确定的周期对应于可听见的至少一部分中的频率时，改变所确定的周期以产生开关控制信号的宽频谱频带。在可听频带中产生具有宽频谱的开关控制信号允许系统利用可听频带中的开关频率。

95. 发明申请

US20080272757A1 POWER SUPPLY DC VOLTAGE OFFSET DETECTOR 有权
标题翻译：电源直流电压偏移检测器
公开(公告)号：US20080272757A1
公开(公告)日：2008-11-06
申请号：US11967277
申请日：2007-12-31
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： G05F1/10
CPC分类号： H02M1/4225 , H03M3/476 , Y02B70/126 , Y02P80/112
摘要： A power supply output voltage direct current (DC) offset detector determines a DC offset in a power supply output voltage signal, and the output voltage signal has a DC component and an alternating current (AC) “ripple” component. Once during each period of the ripple, the DC offset detector determines the DC offset from an output voltage signal using a comparison between the output voltage signal and a reference voltage. In at least one embodiment, from the comparison and during a period of the ripple, the DC offset detector determines an ‘above’ duration for which the ripple is above the reference voltage, determines a ‘below’ duration for which the ripple is below the reference voltage, or both to determine the DC offset of the power supply output voltage signal. The DC offset detector uses the above and/or below duration(s) to determine the DC offset of the output voltage signal.
摘要翻译：电源输出电压直流（DC）偏移检测器确定电源输出电压信号中的直流偏移，输出电压信号具有直流分量和交流（AC）“纹波”分量。一旦在纹波的每个周期期间，直流偏移检测器使用输出电压信号和参考电压之间的比较来确定来自输出电压信号的直流偏移。在至少一个实施例中，从比较起，在纹波周期期间，直流偏移检测器确定纹波高于参考电压的“高于”持续时间，确定纹波低于参考电压或两者以确定电源输出电压信号的直流偏移。 DC偏移检测器使用上述和/或以下持续时间来确定输出电压信号的DC偏移。

96. 发明申请

US20080224636A1 POWER CONTROL SYSTEM FOR CURRENT REGULATED LIGHT SOURCES 有权
标题翻译：电流调节光源功率控制系统
公开(公告)号：US20080224636A1
公开(公告)日：2008-09-18
申请号：US12047262
申请日：2008-03-12
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： H05B39/04 , H05B37/02 , G05F1/00
CPC分类号： H05B33/0815 , H05B33/0818 , Y02B20/347 , Y10S315/04
摘要： A light emitting diode (LED) lighting system includes a PFC and output voltage controller and a LED lighting power system. The controller advantageously operates from an auxiliary voltage less than a link voltage generated by the LED lighting power system. The common reference voltage allows all the components of lighting system to work together. A power factor correction switch and an LED drive current switch are coupled to the common reference node and have control node-to-common node, absolute voltage that allows the controller to control the conductivity of the switches. The LED lighting system can utilize feed forward control to concurrently modify power demand by the LED lighting power system and power demand of one or more LEDs. The LED lighting system can utilize a common current sense device to provide a common feedback signal to the controller representing current in at least two of the LEDs.
摘要翻译：发光二极管（LED）照明系统包括PFC和输出电压控制器以及LED照明电源系统。控制器有利地从小于由LED照明电力系统产生的链路电压的辅助电压进行操作。公共参考电压允许照明系统的所有组件一起工作。功率因数校正开关和LED驱动电流开关耦合到公共参考节点并具有控制节点到公共节点，允许控制器控制开关的电导率的绝对电压。 LED照明系统可以利用前馈控制来同时修改LED照明电源系统的功率需求和一个或多个LED的功率需求。 LED照明系统可以利用公共电流检测装置向控制器提供公共反馈信号，该控制器表示至少两个LED中的电流。

97. 发明申请

US20080224633A1 Lighting System with Lighting Dimmer Output Mapping 有权
标题翻译：照明系统具有照明调光输出映射
公开(公告)号：US20080224633A1
公开(公告)日：2008-09-18
申请号：US11695024
申请日：2007-04-01
申请人： John L. Melanson , John J. Paulos
发明人： John L. Melanson , John J. Paulos
IPC分类号： H05B41/39
CPC分类号： H05B37/0209 , H05B33/0809 , H05B33/0848 , H05B37/02
摘要： A system and method map dimming levels of a lighting dimmer to light source control signals using a predetermined lighting output function. The dimmer generates a dimmer output signal value. At any particular period of time, the dimmer output signal value represents one of multiple dimming levels. In at least one embodiment, the lighting output function maps the dimmer output signal value to a dimming value different than the dimming level represented by the dimmer output signal value. The lighting output function converts a dimmer output signal values corresponding to measured light levels to perception based light levels. A light source driver operates a light source in accordance with the predetermined lighting output function. The system and method can include a filter to modify at least a set of the dimmer output signal values prior to mapping the dimmer output signal values to a new dimming level.
摘要翻译：系统和方法使用预定的照明输出功能将照明调光器的调光水平映射到光源控制信号。调光器产生调光输出信号值。在任何特定时间段，调光器输出信号值表示多个调光电平之一。在至少一个实施例中，照明输出功能将调光器输出信号值映射到与由调光器输出信号值表示的调光电平不同的调光值。照明输出功能将对应于测量光级的调光输出信号值转换为基于感知的光级。光源驱动器根据预定的照明输出功能操作光源。该系统和方法可以包括滤波器，以在将调光器输出信号值映射到新的调光电平之前修改至少一组调光输出信号值。

98. 发明授权

US07408490B2 Calibration of a redundant number system successive approximation analog-to-digital converter 有权
标题翻译：冗余数字系统逐次逼近模数转换器的校准
公开(公告)号：US07408490B2
公开(公告)日：2008-08-05
申请号：US11537872
申请日：2006-10-02
申请人： John L. Melanson , Clinton R. Wolff
发明人： John L. Melanson , Clinton R. Wolff
IPC分类号： H03M1/10
CPC分类号： H03M1/1038 , H03M1/069 , H03M1/1033 , H03M1/468 , H03M1/804
摘要： A system and method calibrate a redundant number system analog-to-digital converter (RNS ADC) using successive approximations of multiple input signals and approximating each input signal at least twice. The RNS ADC includes N analog converter reference elements, each of the analog converter reference elements is associated with a weight in a weight vector W, and N is an integer greater than one. The system and method successively approximate each of M distinct analog input signals twice to generate M respective pairs of successive approximation converter reference element vectors, C1j and C2j,that correspond to digital approximations of the input signals, wherein j ε {0, 1, . . . , M−1}, wherein M is a positive integer. The system and method utilize differences between the successive approximation converter reference element vectors, C1j and C2j to determine a final weight vector WB. Thus, in at least one embodiment, the difference between C1j· WB and C2j· WB can be used to determine the final weight vector WB.
摘要翻译：系统和方法使用多个输入信号的逐次逼近来校准冗余数字系统模数转换器（RNS ADC），并将每个输入信号近似至少两次。 RNS ADC包括N个模拟转换器参考元件，每个模拟转换器参考元件与权重向量 W中的权重相关联，并且N是大于1的整数。该系统和方法连续地近似M个不同的模拟输入信号中的每一个，以产生M个相应的逐次逼近转换器参考元素对，即，OLEYLE =“SLELE”> C 1 < 和 C 对应于数字近似值输入信号，其中j∈{0,1，...，。。，M-1}，其中M为正整数。该系统和方法利用逐次逼近转换器参考元素向量之间的差异，其中 C <1> OSTYLE =“SINGLE”> C j 以确定最终权重向量 W B / SUB>。因此，在至少一个实施例中， > > 之间的差异。 W B B 和 C 。可以使用 W B B来确定最终权重向量“O OYYLE =”SINGLE“> W B B 。

99. 发明申请

US20080144861A1 METHOD AND APPARATUS FOR CONTROLLING A SELECTABLE VOLTAGE AUDIO POWER OUTPUT STAGE 有权
标题翻译：用于控制可选择的电压音频功率输出级的方法和装置
公开(公告)号：US20080144861A1
公开(公告)日：2008-06-19
申请号：US11611069
申请日：2006-12-14
申请人： John L. Melanson , John Christopher Tucker
发明人： John L. Melanson , John Christopher Tucker
IPC分类号： H03F21/00
CPC分类号： H03F1/025
摘要： A method and apparatus for controlling a selectable voltage audio power output stage provides a mechanism for raising the selected power amplifier output voltage in time for the arrival of signal peaks to avoid clipping. Signal peaks may either be delayed by delaying an increase in volume control level or enabling signal compression for a predetermined time period, so that sufficient time is provided for the amplifier power supply to stabilize at a higher operating voltage when an increase of power supply voltage is selected. Alternatively, a signal level may be determined at an upstream source, such as a decoder or filter that provides information in sufficient advance of the arrival of the peaks, and used to control the power supply selection, so that the higher power supply voltage level is selected in advance of arrival of the signal peaks that would otherwise cause clipping at the power amplifier output.
摘要翻译：用于控制可选择的电压音频功率输出级的方法和装置提供了用于在信号峰值到达时及时提升所选择的功率放大器输出电压以避免削波的机制。信号峰值可以通过延迟音量控制电平的增加或在预定时间段内启用信号压缩来延迟，使得当电源电压的增加是放大器电源稳定在较高的工作电压时，提供足够的时间选择。或者，可以在诸如解码器或滤波器的上游源处确定信号电平，所述解码器或滤波器提供足够高的峰值到达之前的信息，并且用于控制电源选择，使得较高的电源电压电平为在信号峰值的到达之前选择，否则将在功率放大器输出端造成限幅。

100. 发明授权

US07382300B1 System-on-chip (SoC) integrated circuit including interleaved delta-sigma analog-to-digital converter (ADC) 有权
标题翻译：系统级芯片（SoC）集成电路，包括交错式Δ-Σ模数转换器（ADC）
公开(公告)号：US07382300B1
公开(公告)日：2008-06-03
申请号：US11564331
申请日：2006-11-29
申请人： Kartik Nanda , John L. Melanson , Timothy Thomas Rueger
发明人： Kartik Nanda , John L. Melanson , Timothy Thomas Rueger
IPC分类号： H03M3/00
CPC分类号： H03M3/346 , H03M3/332 , H03M3/334 , H03M3/43 , H03M3/438 , H03M3/474
摘要： A system-on-chip (SoC) integrated circuit including an interleaved delta-sigma analog to digital converter (ADC) provides for reduced noise in the ADC conversions. The ADC is operated intermittently and the balance of the digital circuits forming the system are halted while the conversions take place. The halted portion of the system may include an output low-pass filter of the ADC. The system may include a processor core or other logic having a clock frequency unrelated to the ADC modulator clock frequency that is not otherwise clock-managed to reduce noise induced in the converter output by the operation of the core or other logic.
摘要翻译：包括交错式Δ-Σ模数转换器（ADC）的片上系统（SoC）集成电路可提供ADC转换中的降低的噪声。 ADC间歇性运行，形成系统的数字电路的平衡在转换发生时停止。系统的暂停部分可以包括ADC的输出低通滤波器。该系统可以包括处理器核心或具有与ADC调制器时钟频率无关的时钟频率的其它逻辑，否则不是由时钟管理以便通过核心或其他逻辑的操作来减少在转换器输出中感应的噪声。

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