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91. 发明申请

US20090035926A1 Methods of Fabricating Silicon Carbide Devices Incorporating Multiple Floating Guard Ring Edge Terminations 有权
标题翻译：制造包含多个浮动保护环边缘终端的碳化硅器件的方法
公开(公告)号：US20090035926A1
公开(公告)日：2009-02-05
申请号：US12195700
申请日：2008-08-21
申请人： Sei-Hyung Ryu , Anant K. Agarwal
发明人： Sei-Hyung Ryu , Anant K. Agarwal
IPC分类号： H01L21/28
CPC分类号： H01L29/1608 , H01L29/0619
摘要： Edge termination for silicon carbide devices has a plurality of concentric floating guard rings in a silicon carbide layer that are adjacent and spaced apart from a silicon carbide-based semiconductor junction. An insulating layer, such as an oxide, is provided on the floating guard rings and a silicon carbide surface charge compensation region is provided between the floating guard rings and is adjacent the insulating layer. Methods of fabricating such edge termination are also provided.
摘要翻译：用于碳化硅器件的边缘终端在碳化硅层中具有与碳化硅基半导体结相邻并间隔开的多个同心浮动保护环。在浮动保护环上设置绝缘层，例如氧化物，并且在浮动保护环之间提供碳化硅表面电荷补偿区，并且与绝缘层相邻。还提供了制造这种边缘终止的方法。

92. 发明授权

US07414268B2 High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities 有权
标题翻译：具有双向阻塞能力的高压碳化硅MOS双极器件
公开(公告)号：US07414268B2
公开(公告)日：2008-08-19
申请号：US11132355
申请日：2005-05-18
申请人： Sei-Hyung Ryu , Jason R. Jenny , Mrinal K. Das , Hudson McDonald Hobgood , Anant K. Agarwal , John W. Palmour
发明人： Sei-Hyung Ryu , Jason R. Jenny , Mrinal K. Das , Hudson McDonald Hobgood , Anant K. Agarwal , John W. Palmour
IPC分类号： H01L31/0312 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7395 , H01L29/1608 , H01L29/66068 , H01L29/66333
摘要： Silicon carbide high voltage semiconductor devices and methods of fabricating such devices are provided. The devices include a voltage blocking substrate. Insulated gate bipolar transistors are provided that have a voltage blocking substrate. Planar and beveled edge termination may be provided.
摘要翻译：提供了碳化硅高压半导体器件及其制造方法。这些器件包括电压阻挡衬底。提供具有电压阻挡衬底的绝缘栅双极晶体管。可以提供平面和斜边缘终止。

93. 发明授权

US07391057B2 High voltage silicon carbide devices having bi-directional blocking capabilities 有权
标题翻译：具有双向阻挡能力的高电压碳化硅器件
公开(公告)号：US07391057B2
公开(公告)日：2008-06-24
申请号：US11131509
申请日：2005-05-18
申请人： Sei-Hyung Ryu , Jason R. Jenny , Mrinal K. Das , Hudson McDonald Hobgood , Anant K. Agarwal , John W. Palmour
发明人： Sei-Hyung Ryu , Jason R. Jenny , Mrinal K. Das , Hudson McDonald Hobgood , Anant K. Agarwal , John W. Palmour
IPC分类号： H01L31/0312
CPC分类号： H01L29/74 , H01L29/0661 , H01L29/1608
摘要： High voltage silicon carbide (SiC) devices, for example, thyristors, are provided. A first SiC layer having a first conductivity type is provided on a first surface of a voltage blocking SiC substrate having a second conductivity type. A first region of SiC is provided on the first SiC layer and has the second conductivity type. A second region of SiC is provided in the first SiC layer. The second region of SiC has the first conductivity type and is adjacent to the first region of SiC. A second SiC layer having the first conductivity type is provided on a second surface, opposite the first surface, of the voltage blocking SiC substrate. First, second and third contacts are provided on the first region of SiC, the second region of SiC and the second SiC layer, respectively. Related methods of fabricating high voltage SiC devices are also provided.
摘要翻译：提供高压碳化硅（SiC）器件，例如晶闸管。具有第一导电类型的第一SiC层设置在具有第二导电类型的压电SiC衬底的第一表面上。 SiC的第一区域设置在第一SiC层上并具有第二导电类型。 SiC的第二区域设置在第一SiC层中。 SiC的第二区域具有第一导电类型并且与SiC的第一区域相邻。具有第一导电类型的第二SiC层设置在压电SiC衬底的与第一表面相对的第二表面上。首先，分别在SiC的第一区域，SiC的第二区域和第二SiC层上设置第二和第三触点。还提供了制造高电压SiC器件的相关方法。

94. 发明授权

US07381992B2 Silicon carbide power devices with self-aligned source and well regions 有权
标题翻译：具有自对准源和阱区的碳化硅功率器件
公开(公告)号：US07381992B2
公开(公告)日：2008-06-03
申请号：US11456642
申请日：2006-07-11
申请人： Sei-Hyung Ryu
发明人： Sei-Hyung Ryu
IPC分类号： H01L29/15
CPC分类号： H01L29/7802 , H01L21/049 , H01L29/1608 , H01L29/66068 , H01L29/7828 , H01L29/7838 , Y10S438/931
摘要： Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices are provided by successively etching a mask layer to provide windows for formation of a source region of a first conductivity type, a buried silicon carbide region of a second conductivity type opposite to the first conductivity type and a second conductivity type well region in a first conductivity type silicon carbide layer. The source region and the buried silicon carbide region are formed utilizing a first window of the mask layer. Then, the well region is formed utilizing a second window of the mask layer, the second window being provided by a subsequent etch of the mask layer having the first window.
摘要翻译：碳化硅半导体器件和制造碳化硅半导体器件的方法通过连续地蚀刻掩模层来提供用于形成第一导电类型的源极区域的窗口，与第一导电类型相反的第二导电类型的掩埋碳化硅区域型和第一导电型碳化硅层中的第二导电类型阱区。利用掩模层的第一窗口形成源区和掩埋碳化硅区。然后，利用掩模层的第二窗口形成阱区，第二窗口通过随后蚀刻具有第一窗口的掩模层来提供。

95. 发明申请

US20070066039A1 METHODS OF PROCESSING SEMICONDUCTOR WAFERS HAVING SILICON CARBIDE POWER DEVICES THEREON 有权
标题翻译：加工具有硅碳膜电源器件的半导体晶体管的方法
公开(公告)号：US20070066039A1
公开(公告)日：2007-03-22
申请号：US11531975
申请日：2006-09-14
申请人： Anant Agarwal , Sei-Hyung Ryu , Matthew Donofrio
发明人： Anant Agarwal , Sei-Hyung Ryu , Matthew Donofrio
IPC分类号： H01L21/425
CPC分类号： H01L21/0485 , H01L21/0495 , H01L21/268 , H01L29/6606 , Y10S438/931
摘要： Methods of forming a silicon carbide semiconductor device are disclosed. The methods include forming a semiconductor device at a first surface of a silicon carbide substrate having a first thickness, and mounting a carrier substrate to the first surface of the silicon carbide substrate. The carrier substrate provides mechanical support to the silicon carbide substrate. The methods further include thinning the silicon carbide substrate to a thickness less the first thickness, forming a metal layer on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate, and locally annealing the metal layer to form an ohmic contact on the thinned silicon carbide substrate opposite the first surface of the silicon carbide substrate. The silicon carbide substrate is singulated to provide a singulated semiconductor device.
摘要翻译：公开了形成碳化硅半导体器件的方法。所述方法包括在具有第一厚度的碳化硅衬底的第一表面上形成半导体器件，以及将载体衬底安装到碳化硅衬底的第一表面上。载体衬底为碳化硅衬底提供机械支撑。所述方法还包括将碳化硅衬底减薄至小于第一厚度的厚度，在与碳化硅衬底的第一表面相对的稀薄的碳化硅衬底上形成金属层，并局部退火金属层以在其上形成欧姆接触薄碳化硅衬底与碳化硅衬底的第一表面相对。将碳化硅衬底分离以提供单片半导体器件。

96. 发明授权

US06979863B2 Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same 有权
标题翻译：具有集成反平行结屏障的碳化硅MOSFET肖特基续流二极管及其制造方法
公开(公告)号：US06979863B2
公开(公告)日：2005-12-27
申请号：US10422554
申请日：2003-04-24
申请人： Sei-Hyung Ryu
发明人： Sei-Hyung Ryu
IPC分类号： H01L21/04 , H01L29/24 , H01L29/78 , H01L29/872 , H01L29/76
CPC分类号： H01L29/7806 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/872
摘要： Silicon carbide semiconductor devices and methods of fabricating silicon carbide semiconductor devices have a silicon carbide DMOSFET and an integral silicon carbide Schottky diode configured to at least partially bypass a built in diode of the DMOSFET. The Schottky diode may be a junction barrier Schottky diode and may have a turn-on voltage lower than a turn-on voltage of a built-in body diode of the DMOSFET. The Schottky diode may have an active area less than an active area of the DMOSFET.
摘要翻译：碳化硅半导体器件和制造碳化硅半导体器件的方法具有碳化硅DMOSFET和被配置为至少部分地旁路DMOSFET的内置二极管的整体式碳化硅肖特基二极管。肖特基二极管可以是结势垒肖特基二极管，并且可以具有低于DMOSFET的内置体二极管的导通电压的导通电压。肖特基二极管可以具有小于DMOSFET的有效面积的有效面积。

97. 发明授权

US09984894B2 Forming SiC MOSFETs with high channel mobility by treating the oxide interface with cesium ions 有权
公开(公告)号：US09984894B2
公开(公告)日：2018-05-29
申请号：US13196994
申请日：2011-08-03
申请人： Sarit Dhar , Sei-Hyung Ryu , Anant Agarwal , John Robert Williams
发明人： Sarit Dhar , Sei-Hyung Ryu , Anant Agarwal , John Robert Williams
IPC分类号： H01L21/336 , H01L21/3115 , H01L21/04 , H01L29/40 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/16 , H01L29/08
CPC分类号： H01L21/3115 , H01L21/049 , H01L29/0878 , H01L29/1608 , H01L29/408 , H01L29/51 , H01L29/66068 , H01L29/78 , H01L29/7802
摘要： Methods of forming a semiconductor structure include providing an insulation layer on a semiconductor layer and diffusing cesium ions into the insulation layer from a cesium ion source outside the insulation layer. A MOSFET including an insulation layer treated with cesium ions may exhibit increased inversion layer mobility.

98. 发明授权

US08901699B2 Silicon carbide junction barrier Schottky diodes with suppressed minority carrier injection 有权
标题翻译：具有抑制少数载流子注入的碳化硅结屏障肖特基二极管
公开(公告)号：US08901699B2
公开(公告)日：2014-12-02
申请号：US11126816
申请日：2005-05-11
申请人： Sei-Hyung Ryu , Anant K. Agarwal
发明人： Sei-Hyung Ryu , Anant K. Agarwal
IPC分类号： H01L29/47 , H01L29/872 , H01L29/66 , H01L29/06 , H01L29/16
CPC分类号： H01L29/6606 , H01L29/0615 , H01L29/0619 , H01L29/1608 , H01L29/872
摘要： Integral structures that block the current conduction of the built-in PiN diode in a junction barrier Schottky (JBS) structure are provided. A Schottky diode may be incorporated in series with the PiN diode, where the Schottky diode is of opposite direction to that of the PiN diode. A series resistance or and insulating layer may be provided between the PiN diode and a Schottky contact. Silicon carbide Schottky diodes and methods of fabricating silicon carbide Schottky diodes that include a silicon carbide junction barrier region disposed within a drift region of the diode are also provided. The junction barrier region includes a first region of silicon carbide having a first doping concentration in the drift region of the diode and a second region of silicon carbide in the drift region and disposed between the first region of silicon carbide and a Schottky contact of the Schottky diode. The second region is in contact with the first region of silicon carbide and the Schottky contact. The second region of silicon carbide has a second doping concentration that is less than the first doping concentration.
摘要翻译：提供阻塞内部PiN二极管在结屏障肖特基（JBS）结构中的电流传导的积分结构。肖特基二极管可以与PiN二极管串联，其中肖特基二极管与PiN二极管的方向相反。可以在PiN二极管和肖特基接触之间提供串联电阻或绝缘层。还提供了碳化硅肖特基二极管和制造碳化硅肖特基二极管的方法，其包括设置在二极管的漂移区域内的碳化硅结壁垒区域。结阻挡区域包括在二极管的漂移区域中具有第一掺杂浓度的碳化硅的第一区域和漂移区域中的第二碳化硅区域，并且设置在碳化硅的第一区域与肖特基的肖特基接触之间二极管。第二区域与碳化硅的第一区域和肖特基接触部接触。碳化硅的第二区域具有小于第一掺杂浓度的第二掺杂浓度。

99. 发明授权

US08546874B2 Power switching semiconductor devices including rectifying junction-shunts 有权
标题翻译：功率开关半导体器件包括整流结分路
公开(公告)号：US08546874B2
公开(公告)日：2013-10-01
申请号：US13267966
申请日：2011-10-07
申请人： Allen Hefner , Sei-Hyung Ryu , Anant Agarwal
发明人： Allen Hefner , Sei-Hyung Ryu , Anant Agarwal
IPC分类号： H01L29/76
CPC分类号： H01L29/7803 , H01L21/0465 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/41766 , H01L29/6606 , H01L29/66068 , H01L29/7802 , H01L29/7828 , H01L29/861
摘要： A semiconductor device includes a drift layer and a body region that forms a p-n junction with the drift layer. A contactor region is in the body region, and a shunt channel region extends through the body region from the contactor region to the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse bias the p-n junction between the drift region and the body region.
摘要翻译：半导体器件包括漂移层和与漂移层形成p-n结的体区。接触器区域在体区域中，并且分流通道区域从接触器区域延伸穿过体区域到漂移层。分流沟道区域具有选择的长度，厚度和掺杂浓度，使得：1）当跨越第一和第二端子施加零电压时，并联沟道区域完全耗尽，2）并联沟道在小于内部电位漂移层到体区pn结，和/或3）并联通道对于反向偏置漂移区域和体区之间的pn结的电压是不导通的。

100. 发明申请

US20120223330A1 SEMICONDUCTOR DEVICE HAVING HIGH PERFORMANCE CHANNEL 有权
标题翻译：具有高性能通道的半导体器件
公开(公告)号：US20120223330A1
公开(公告)日：2012-09-06
申请号：US13039441
申请日：2011-03-03
申请人： Sarit Dhar , Sei-Hyung Ryu , Lin Cheng , Anant Agarwal
发明人： Sarit Dhar , Sei-Hyung Ryu , Lin Cheng , Anant Agarwal
IPC分类号： H01L29/161 , H01L21/22
CPC分类号： H01L29/107 , H01L21/225 , H01L29/1608 , H01L29/66068 , H01L29/66477 , H01L29/66568
摘要： Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior.
摘要翻译：公开了具有高性能通道的半导体器件及其制造方法。优选地，半导体器件是金属氧化物半导体（MOS）器件，并且甚至更优选半导体器件是碳化硅（SiC）MOS器件。在一个实施例中，半导体器件包括第一导电类型的SiC衬底，第二导电类型的第一阱，第二导电类型的第二阱以及形成在第二导电类型的表面处的第二导电类型的表面扩散沟道半导体器件在第一和第二阱之间。控制表面扩散通道的深度和掺杂浓度，以便在处于导通状态同时保持导通状态或阈值时，与没有表面扩散沟道区的相同半导体器件相比，为半导体器件提供增加的载流子迁移率，电压提供常态动作。

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