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91. 发明授权

US06633499B1 Method for reducing voltage drops in symmetric array architectures 有权
标题翻译：降低对称阵列结构中电压降的方法
公开(公告)号：US06633499B1
公开(公告)日：2003-10-14
申请号：US09536125
申请日：2000-03-28
申请人： Boaz Eitan , Eduardo Maayan
发明人： Boaz Eitan , Eduardo Maayan
IPC分类号： G11C1604
CPC分类号： G11C7/18 , G11C11/5671 , G11C16/0475 , G11C16/0491 , G11C16/24 , H01L27/115
摘要： A symmetric segmented array has select transistors and column select transistors. At least one of the select and/or column select transistors is a low threshold voltage device. Alternatively, at least one select transistor and/or column select transistor of the array has a channel length shorter than a standard channel length of a process.
摘要翻译：对称分段阵列具有选择晶体管和列选择晶体管。选择和/或列选择晶体管中的至少一个是低阈值电压器件。或者，阵列的至少一个选择晶体管和/或列选择晶体管的沟道长度短于工艺的标准沟道长度。

92. 发明授权

US06566699B2 Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping 有权
公开(公告)号：US06566699B2
公开(公告)日：2003-05-20
申请号：US09939570
申请日：2001-08-28
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： H01L31119
CPC分类号： G11C16/14 , G11C16/10 , G11C16/26 , H01L21/28282 , H01L29/792
摘要： A method of enhancing erasure of a cell having a non-conductive charge trapping layer, the cell having a gate generally over the charge trapping layer includes programming the cell to minimize the width of a trapping region within the charge trapping layer by reading with a minimum voltage on the gate in a direction opposite that of programming.

93. 发明授权

US06233180B1 Device for determining the validity of word line conditions and for delaying data sensing operation 有权
标题翻译：用于确定字线条件有效性和延迟数据传感操作的装置
公开(公告)号：US06233180B1
公开(公告)日：2001-05-15
申请号：US09244454
申请日：1999-02-04
申请人： Boaz Eitan , Oleg Dadashev
发明人： Boaz Eitan , Oleg Dadashev
IPC分类号： G11C708
CPC分类号： G11C7/22 , G11C7/06 , G11C8/18
摘要： A delay device for delaying the activation of a sensing indication signal includes a reference word-line, a reference word-line driver, and a comparator. The reference word-line driver is controlled by a strobe signal, and is connected to the reference word-line and a reference word-line voltage. Additionally, when so indicated by the strobe signal, the reference word-line driver provides the reference word-line voltage to the reference word-line. The comparator is connected to the reference word-line and to the reference word-line voltage and activates the sensing indication signal when the voltage on the reference word-line is at least equal to a predetermined function of the reference word-line voltage.
摘要翻译：用于延迟感测指示信号的激活的延迟装置包括参考字线，参考字线驱动器和比较器。参考字线驱动器由选通信号控制，并连接到参考字线和参考字线电压。此外，当由选通信号指示时，参考字线驱动器将参考字线电压提供给参考字线。比较器连接到参考字线和参考字线电压，并且当参考字线上的电压至少等于参考字线电压的预定函数时，激活感测指示信号。

94. 发明授权

US6134156A Method for initiating a retrieval procedure in virtual ground arrays 有权
标题翻译：在虚拟地面阵列中启动检索过程的方法
公开(公告)号：US6134156A
公开(公告)日：2000-10-17
申请号：US246776
申请日：1999-02-04
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： G11C16/06 , G11C16/04 , G11C16/26
CPC分类号： G11C16/0491 , G11C16/26
摘要： A method for detecting the content of a selected memory cell in a memory cell array includes the steps of charging a drain of the selected memory cell to a ground potential, charging a source of the selected memory cell to a predetermined voltage potential, detecting the voltage level on the drain and comparing the detected voltage level with a reference voltage level, thereby producing a comparison result.
摘要翻译：一种用于检测存储单元阵列中所选择的存储单元的内容的方法包括以下步骤：将所选存储单元的漏极充电到地电位，将所选存储单元的源充电到预定电压电位，检测电压电平，并将检测到的电压电平与参考电压电平进行比较，从而产生比较结果。

95. 发明授权

US6030871A Process for producing two bit ROM cell utilizing angled implant 失效
标题翻译：使用倾斜植入物生产两位ROM单元的方法
公开(公告)号：US6030871A
公开(公告)日：2000-02-29
申请号：US72462
申请日：1998-05-05
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： G11C11/56 , G11C16/04 , H01L21/265 , H01L21/8246 , H01L27/112 , H01L21/8236
CPC分类号： H01L27/11266 , G11C11/56 , G11C11/5671 , G11C11/5692 , G11C16/0475 , H01L21/26586 , H01L27/112
摘要： A dual bit read only memory cell has two bits separately stored in two different areas of the channel, such as the left and right bit line junctions of the channel. A programmed bit has a threshold pocket implant self-aligned to its bit line junction and an unprogrammed bit has no such implant. An array of such cells is manufactured by laying down a bit line mask and separately programming the two bit line junctions. For each bit line junction, the bit line junctions which are to remain unprogrammed are first covered, with a junction mask, after which the array is exposed to a threshold pocket implant at a 15-45.degree. angle, to the right or to the left. The junction mask is removed and the process repeated for the other bit line junction. Finally, the bit line mask is removed. In an alternative embodiment, the threshold pocket implant is two implants, of two different materials.
摘要翻译：双位只读存储器单元具有分别存储在通道的两个不同区域中的两个位，例如通道的左和右位线结。编程的位具有与其位线结自对准的阈值口袋注入，并且未编程的位没有这种植入物。通过放置位线掩模并分别编程两个位线结来制造这样的单元阵列。对于每个位线结，首先用结合掩模覆盖要保持未编程的位线结，然后将阵列暴露于15-45°角的阈值口袋注入，向右或向左。结合掩模被去除，并且对于另一位线结重复该过程。最后，位线掩模被删除。在替代实施例中，阈值口袋植入物是两种不同材料的植入物。

96. 发明授权

US5966603A NROM fabrication method with a periphery portion 失效
标题翻译：具有外围部分的NROM制造方法
公开(公告)号：US5966603A
公开(公告)日：1999-10-12
申请号：US873384
申请日：1997-06-11
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： H01L21/8246
CPC分类号： H01L27/11568
摘要： A method of fabricating a nitride read only memory (NROM) chip creates an oxide-nitride-oxide (ONO) layer on a substrate and etches the ONO layer within the memory portion of the chip into columns. Bit lines are implanted between columns after which bit line oxides are generated on top of the bit lines with the thickness of the bit line oxides being independent of the thickness of the bottom oxide. The thickness of a gate oxide layer in a periphery portion of the chip is also relatively independent of the thicknesses of the other oxides. Finally, rows of polysilicon or polysilicide are formed perpendicular to and on top of the bit line oxides and the ONO columns.
摘要翻译：制造氮化物只读存储器（NROM）芯片的方法在衬底上产生氧化物 - 氮化物 - 氧化物（ONO）层，并将芯片的存储器部分内的ONO层蚀刻成列。将位线注入列之后，在位线之上产生位线氧化物，位线氧化物的厚度与底部氧化物的厚度无关。芯片周边部分中的栅极氧化物层的厚度也相对独立于其它氧化物的厚度。最后，多晶硅或聚硅化物行垂直于位线氧化物和ONO柱形成。

97. 发明授权

US5862076A Fast EPROM array 失效
标题翻译：快速EPROM阵列
公开(公告)号：US5862076A
公开(公告)日：1999-01-19
申请号：US908595
申请日：1992-06-30
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： G11C17/00 , G11C7/18 , G11C16/04 , G11C16/26 , H01L21/8247 , H01L27/115 , G11C16/06
CPC分类号： G11C16/26 , G11C16/0425 , G11C16/0491 , G11C7/18 , H01L27/115
摘要： Each read line in a memory array containing a plurality of alternating bit lines and read lines with columns of memory cells therebetween, is broken into a plurality of electrically isolatable segments. As a result, the capacitance associated with each read line is significantly reduced and the speed of reading information from or writing information into a memory cell is significantly increased while at the same time not decreasing the density of the array.
摘要翻译：包含多个交替位线的存储器阵列中的每条读取线和其间具有存储器单元列的读取线被分解成多个电隔离段。结果，与每条读取线相关联的电容显着降低，并且从信息读取信息或将信息写入存储器单元的速度显着增加，同时不降低阵列的密度。

98. 发明授权

US5557229A Apparatus and method for producing an output signal from a memory array 失效
标题翻译：用于从存储器阵列产生输出信号的装置和方法
公开(公告)号：US5557229A
公开(公告)日：1996-09-17
申请号：US242929
申请日：1994-05-16
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： H03K19/003 , H03K19/017 , H03K19/00
CPC分类号： H03K19/01728 , H03K19/00361
摘要： An output device and method of operating it are disclosed. The output device includes a output control unit and an output buffer unit. The output control unit produces a data release (INR) signal after producing an output release (OR) signal, for example, by delaying the OR signal. The INR signal causes release of an output signal from a sense amplifier, resulting in a data signal. The output buffer includes n- and p-channel switching transistors and control units controlling their gates. In response to activation of the OR signal, the control units bring the voltage of the gates of the switching transistors to respectively slightly above and slightly below the threshold levels of their gates. In response to the data signal, the control units fully activate one of the switching transistors and deactivate the other of the switching transistors depending on the voltage level of the data signal. The speed with which the control units respond to the data signal is controlled.
摘要翻译：公开了一种输出装置及其操作方法。输出装置包括输出控制单元和输出缓冲单元。输出控制单元在产生输出释放（OR）信号之后例如通过延迟OR信号来产生数据释放（INR）信号。 INR信号导致从读出放大器释放输出信号，导致数据信号。输出缓冲器包括n沟道开关晶体管和p沟道开关晶体管以及控制其栅极的控制单元。响应于OR信号的激活，控制单元使开关晶体管的栅极的电压分别略高于并稍低于其栅极的阈值水平。响应于数据信号，控制单元完全启动开关晶体管之一，并根据数据信号的电压电平使另一个开关晶体管停用。控制单元响应数据信号的速度受到控制。

99. 发明授权

US5453636A MOS SRAM cell with open base bipolar loads 失效
标题翻译：具有开路基极双极性负载的MOS SRAM单元
公开(公告)号：US5453636A
公开(公告)日：1995-09-26
申请号：US291252
申请日：1994-08-16
申请人： Boaz Eitan , Alexander Shubat
发明人： Boaz Eitan , Alexander Shubat
IPC分类号： H01L27/11 , H01L27/02
CPC分类号： H01L27/11 , Y10S257/903
摘要： An SRAM cell includes an open-base, bipolar transistor serving as a load device and one pull-down transistor having an associated leakage current. The amplification .beta. of the bipolar transistor controls the amount of load current through the bipolar transistor. The bipolar transistor provides the necessary load current to ensure the SRAM cell maintains its logic state.
摘要翻译： SRAM单元包括用作负载器件的开放式双极晶体管和具有相关联的漏电流的一个下拉晶体管。双极晶体管的放大率β控制通过双极晶体管的负载电流量。双极晶体管提供必要的负载电流，以确保SRAM单元保持其逻辑状态。

100. 发明授权

US5204835A EPROM virtual ground array 失效
标题翻译： EPROM VIRTUAL GROUND ARRAY
公开(公告)号：US5204835A
公开(公告)日：1993-04-20
申请号：US539657
申请日：1990-06-13
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： G11C17/00 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0491
摘要： An electrically programmable read only memory contains alternating metal bit lines and diffused bit lines. Each diffused bit line is broken into a plurality of segments. Each of the segments of the diffused bit line comprises a virtual source. A multiplicity of floating gate transistors are arranged in rows and columns. The floating gate transistors in each column are divided into M groups of N floating gate transistors each. The floating gate transistors in the n.sup.th and the (n+1).sup.th columns, where n is an odd integer given by 1.ltoreq.n.ltoreq.N and (N+1) is the maximum number of columns in the array are connected to the segments of one diffused bit line placed between the n.sup.th and the (n+1).sup.th columns. At least one first transfer transistor is arranged to connect one segment comprising a virtual source to a first metal bit line. The first metal bit line functions as the source for the N floating gate transistors in the (n+1).sup.th column connected to said one segment. At least one second transfer transistor connects the same one segment comprising a virtual source to a second metal bit line. The second metal bit line functions as a source for the N floating gate transistors in the n.sup.th column connected to said one segment. The removal of each select transistor from the cell where it previously resided in series with its corresponding floating gate transistor, and the combining of a plurality of select transistors into one select transistor substantially reduces the area taken by each memory cell in the array.

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